Re: [PATCH v2 10/15] dt-bindings: iio: adc: adi,ad4134: Document external multiplexer usage

[Jonathan Cameron <jic23@kernel.org>]

On Tue, 15 Sep 2026 16:15:05 -0300
Marcelo Schmitt <marcelo.schmitt@analog.com> wrote:

> The AD4134 design has two data interfaces. One interface allows register
> access for device configuration while the other (separate interface)
> provides ADC sample data. One way of handling both peripheral interfaces is
> to merge them into a single SPI interface by switching between register
> access and sample access according to device user requests. Though, such
> solution requires extra hardware, external to the ADC chip. The access mode
> switch can be done with an external multiplexer selecting either AD4134 SDO
> or AD4134 DOUT0 to connect to the controller. The external multiplexer
> becomes part of hardware requested for AD4134 device operation and thus
> must be provided for operating the peripheral in such merged interface
> schema. Still, there are alternative ways of handling the two AD4134 data
> interfaces so the multiplexer is not always required.
> 
> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
> ---
> New patch.
> 
> Detailed reasoning for the external multiplexer usage.
> 
> Before coming to the current solution, the following configuration was tried.
> 
>   +-----------------------+                           +-----------------+
>   |       AD4134          |                           | SPI Controller  |
>   |                       |                           |                 |
>   | SPI interface         |                           |                 |
>   | for register     SCLK |<--------------------------| SCLK            |
>   | access             CS |<--------------------------| CS              |
>   |                   SDI |<--------------------------| SDO             |
>   |                   SDO |---+                       |                 |
>   |                       |   |                       |                 |
>   | Data interface  DOUT0 |---+---------------------->| SDI0            |
>   | for ADC data    DOUT1 |-------------------------->| SDI1            |
>   | read back       DOUT2 |-------------------------->| SDI2            |
>   |                 DOUT3 |-------------------------->| SDI3            |
>   |                 DCLK  |<--------------------------| DCLK
>   |                 ODR   |<------------------+    +->| Offload Trigger |
>   +-----------------------+                   |    |  +-----------------+
>                                               |    +--| PWM1            |
>                                               +-------| PWM0            |
>                                               +-------| GPIO            |
>                                                       +-----------------+
> 
> Though, because DOUT0 never goes high-Z, the DOUT0 pin keeps driving the data
> line, causing register reads to fail. 
> 
> Alternatively, we could have something like
> 
>   +-----------------------+                           +-----------------+
>   |       AD4134          |                           | SPI Controller  |
>   |                       |                           |                 |
>   | SPI interface         |                           |                 |
>   | for register     SCLK |<--------------------------| SCLK            |
>   | access             CS |<--------------------------| CS              |
>   |                   SDI |<--------------------------| SDO             |
>   |                   SDO |-------------------------->| SDI0            |
>   |                       |                           |                 |
>   | Data interface  DOUT0 |-------------------------->| SDI1            |
>   | for ADC data    DOUT1 |-------------------------->| SDI2            |
>   | read back       DOUT2 |-------------------------->| SDI3            |
>   |                 DOUT3 |-------------------------->| SDI4            |
>   |                 DCLK  |<--------------------------| DCLK
>   |                 ODR   |<------------------+    +->| Offload Trigger |
>   +-----------------------+                   |    |  +-----------------+
>                                               |    +--| PWM1            |
>                                               +-------| PWM0            |
>                                               +-------| GPIO            |
>                                                       +-----------------+
> 
> The downside of the above is the peripheral would need fine-grained config of
> controller SDI lines to only read SDI0 for register access, and only read SDI1,
> SDI2, SDI3, SDI4 for ADC sample data (currently available
> SPI_MULTI_LANE_MODE_STRIPE reads from all SDI lines).
> 
> The currently proposed solution looks like the following
> 
>   +-----------------------+                         +-----------------+
>   |         AD4134        |                         | SPI Controller  |
>   |                       |                         |                 |
>   | SPI interface    SCLK |<------------------------| SCLK            |
>   | for register       CS |<------------------------| CS              |
>   | access            SDI |<------------------------| SDO             |
>   |                   SDO |------->|¯¯¯¯\           |                 |
>   |                       |        |MUX  >--------->| SDI0            |
>   | Data interface  DOUT0 |------->|____/           |                 |
>   | for ADC sample        |          ^              |                 |
>   | data read       DOUT1 |------------------------>| SDI1            |
>   |                 DOUT2 |------------------------>| SDI2            |
>   |                 DOUT3 |------------------------>| SDI3            |
>   |                  DCLK |<------------------------| DCLK            |
>   |                   ODR |<----------------+    +->| Offload Trigger |
>   +-----------------------+          |      |    |  +-----------------+
>                                      |      |    +--| PWM1            |
>                                      |      +-------| PWM0            |
>                                      |      +-------| GPIO0           |
>                                      +--------------| GPIO1           |
>                                                     +-----------------+
> 
> By being able to mux between AD4134 SDO and AD4134 DOUT0, the peripheral can be
> connected to a single bus such that controllers able to read from multiple lines
> will be able to gather ADC sample data from all SDI lines (SPI_MULTI_LANE_MODE_STRIPE).
> With that, AD4134 maximum data throughput can be supported with what is already
> available from the SPI core. See additional details on the AD4134 IIO
> documentation (patch 15).
> 
> Yet another possibility would be to have the peripheral connecting to two buses.
> 
>   +-----------------------+                           +-----------------+
>   |       AD4134          |                           | SPI Controller A|
>   |                       |                           |                 |
>   | SPI interface    SCLK |<--------------------------| SCLK            |
>   | for register       CS |<--------------------------| CS              |
>   | access            SDI |<--------------------------| SDO             |
>   |                   SDO |-------------------------->| SDI             |
>   |                       |                           +-----------------+
>   |                       |                           | SPI Controller B|
>   |                       |                           |                 |
>   | Data interface  DOUT0 |-------------------------->| SDI0            |
>   | for ADC sample  DOUT1 |-------------------------->| SDI1            |
>   | data read       DOUT2 |-------------------------->| SDI2            |
>   |                 DOUT3 |-------------------------->| SDI3            |
>   |                 DCLK  |<--------------------------| DCLK            |
>   |                 ODR   |<------------------+    +->| Offload Trigger |
>   +-----------------------+                   |    |  +-----------------+
>                                               |    +--| PWM1            |
>                                               +-------| PWM0            |
>                                               +-------| GPIO            |
>                                                       +-----------------+
> 
> That may be a fallback option if what's currently being proposed fails to comply
> to Linux code standards.

I'm not against the MUX option but would imagine anyone reading
the datasheet is at least someone likely to choose this last version.
Still until we have a user for that as far as I am concerned the mux
one is fine.

> 
> 
>  .../devicetree/bindings/iio/adc/adi,ad4134.yaml    | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
> index 012e09decf7a..d89134ce4af6 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
> @@ -104,6 +104,20 @@ properties:
>        GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
>      maxItems: 1
>  
> +  mux-states:
> +    description:
> +      mux controller node to route SDO and DOUT0 signals from peripheral to
> +      controller.
> +    maxItems: 2
> +
> +  mux-state-names:
> +    description:
> +      mux state names for routing SDO and DOUT0 signals from peripheral to
> +      controller.
> +    items:
> +      - const: data_read
> +      - const: reg_access
Throw in an example.

Jonathan

> +
>    adi,asrc-mode:
>      $ref: /schemas/types.yaml#/definitions/string
>      description: