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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93beda70a1esm612157385a.11.2026.09.21.04.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 04:55:14 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1x8cc5-00000006EDj-1rtR; Mon, 21 Sep 2026 08:55:13 -0300 Date: Mon, 21 Sep 2026 08:55:13 -0300 From: Jason Gunthorpe To: Robin Murphy Cc: Guanghui Feng , kevin.tian@intel.com, alex@shazbot.org, joro@8bytes.org, will@kernel.org, iommu@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/2] iommu: Reserve PCI host bridge MMIO windows for IOVA Message-ID: <20260921115513.GK11599@ziepe.ca> References: <20260921070234.897736-1-guanghuifeng@linux.alibaba.com> <20260921103922.1113752-1-guanghuifeng@linux.alibaba.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Sep 21, 2026 at 12:24:13PM +0100, Robin Murphy wrote: > On 21/09/2026 11:39 am, Guanghui Feng wrote: > > The DMA IOVA layer reserves PCI host bridge MMIO windows via > > iova_reserve_pci_windows() to keep IOVA allocations from overlapping > > those address ranges. As commit fade1ec055dc ("iommu/dma: Avoid PCI > > host bridge windows") explains, a host bridge may interpret addresses > > falling within its MMIO windows as peer-to-peer DMA, leading to > > faults, data corruption, or DMA transactions being misrouted to the > > wrong PCIe device. This is especially dangerous when a device sits > > behind a PCIe switch and ACS Upstream Forwarding is not fully enabled. > > > > Passthrough paths that let userspace pick IOVAs did not honour these > > windows: VFIO type1 and iommufd only excluded IOMMU driver-level > > reserved regions (RMRR, unity maps, MSI), not PCI host bridge MMIO > > windows. > > This was intentional - I forget where the exact discussion happened, but at > the time we decided that exposing reserved regions for entire windows was > the wrong thing to do, as being pessimistically inaccurate might be OK for > the internal DMA API, but restricting userspace is another matter, and I > think the consensus was that it wasn't really the IOMMU layer's job to get > deep into PCI details anyway. Such "accidental" P2P can only happen within a > group that's assigned to VFIO as a whole, so IIRC the conclusion was that > users should already have enough information at the VFIO level to avoid BAR > addresses if they need to. Yes, but we never did a a very good job to make the information visible to the VFIO userspace level, and I don't think anyone ever implemented some sysfs parsing to try to get it. It would be a nice improvement to expose these pessimistic ranges to userspace through iommufd so it can choose to opt into them if it wants. Some kind of helper that the dma-iommu.c and iommufd can call perhaps. Jason