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[2a02:3100:1c91:bf00:219:99ff:feb2:2458]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fda0ce29fsm4986905e9.6.2026.09.21.14.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 14:47:41 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Phil Dennis-Jordan , Alistair Francis , Peter Maydell , Alexander Graf , Jason Wang , qemu-arm@nongnu.org, Pierrick Bouvier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bernhard Beschow , Jean-Christophe Dubois , Gaurav Sharma Subject: [PATCH 11/42] hw/arm/fsl-imx25: Derive from TYPE_SYS_BUS_DEVICE Date: Mon, 21 Sep 2026 23:46:39 +0200 Message-ID: <20260921214710.29422-12-shentey@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260921214710.29422-1-shentey@gmail.com> References: <20260921214710.29422-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:30::10; envelope-from=shentey@gmail.com; helo=mail-wr2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Deriving from TYPE_SYS_BUS_DEVICE fixes the SoC object to be reset upon machine reset. Signed-off-by: Bernhard Beschow --- include/hw/arm/fsl-imx25.h | 5 ++--- hw/arm/fsl-imx25.c | 7 +------ hw/arm/imx25_pdk.c | 2 +- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index b68d4334a0..4bb4d5b3e5 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -29,6 +29,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/chipidea.h" #include "hw/watchdog/wdt_imx2.h" +#include "hw/core/sysbus.h" #include "system/memory.h" #include "target/arm/cpu.h" #include "qom/object.h" @@ -45,10 +46,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX25State, FSL_IMX25) #define FSL_IMX25_NUM_USBS 2 struct FslIMX25State { - /*< private >*/ - DeviceState parent_obj; + SysBusDevice parent_obj; - /*< public >*/ ARMCPU cpu; IMXAVICState avic; IMX25CCMState ccm; diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 7f65f4ca4b..efb22359c5 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -317,16 +317,11 @@ static void fsl_imx25_class_init(ObjectClass *oc, const void *data) device_class_set_props(dc, fsl_imx25_properties); dc->realize = fsl_imx25_realize; dc->desc = "i.MX25 SOC"; - /* - * Reason: uses serial_hds in realize and the imx25 board does not - * support multiple CPUs - */ - dc->user_creatable = false; } static const TypeInfo fsl_imx25_type_info = { .name = TYPE_FSL_IMX25, - .parent = TYPE_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(FslIMX25State), .instance_init = fsl_imx25_init, .class_init = fsl_imx25_class_init, diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 243c30a67e..6ce3e35ee3 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -72,7 +72,7 @@ static void imx25_pdk_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_FSL_IMX25); - qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->soc), &error_fatal); /* We need to initialize our memory */ if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { -- 2.55.0