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Tue, 22 Sep 2026 09:02:08 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v1 10/19] hw/usb/aspeed-udc: Mask the reserved bits on register writes Thread-Topic: [PATCH v1 10/19] hw/usb/aspeed-udc: Mask the reserved bits on register writes Thread-Index: AQHdSnELYWGsFRo56EGJRFVl2z0+aQ== Date: Tue, 22 Sep 2026 09:02:08 +0000 Message-ID: <20260922090154.1792077-11-jamin_lin@aspeedtech.com> References: <20260922090154.1792077-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260922090154.1792077-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|TY1PPFFE5B965AC:EE_ x-ms-office365-filtering-correlation-id: 83f07ad7-696f-4f7a-49e1-08df18882e6e x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Writes to the interrupt registers were not masked, so a guest could set=0A= a reserved bit and read it back. The hardware returns 0 for those.=0A= =0A= Mask each one to the bits the datasheet marks read/write:=0A= =0A= UDC_IER 17, 16, 8:6, 4:0=0A= UDC_ISR 8:6, 4:0=0A= UDC_EP_ACK_IER 3:0=0A= UDC_EP_NAK_IER 3:0=0A= UDC_EP_ACK_ISR 3:0=0A= UDC_EP_NAK_ISR 3:0=0A= =0A= UDC_ISR bits 17 and 16 summarise the endpoint pool. They are read only,=0A= so a write cannot clear them.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/usb/aspeed-udc.c | 12 +++++++++++-=0A= 1 file changed, 11 insertions(+), 1 deletion(-)=0A= =0A= diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c=0A= index 355512822b..95fe823534 100644=0A= --- a/hw/usb/aspeed-udc.c=0A= +++ b/hw/usb/aspeed-udc.c=0A= @@ -319,14 +319,24 @@ static void aspeed_udc_write(void *opaque, hwaddr off= set, uint64_t data,=0A= s->regs[R_UDC_FUNC_CTRL] =3D val;=0A= break;=0A= case R_UDC_IER:=0A= + val &=3D 0x000301df;=0A= + s->regs[reg] =3D val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= + case R_UDC_ISR:=0A= + val &=3D 0x000001df;=0A= + s->regs[reg] &=3D ~val;=0A= + aspeed_udc_update_irq(s);=0A= + break;=0A= case R_UDC_EP_ACK_IER:=0A= case R_UDC_EP_NAK_IER:=0A= + val &=3D 0x0000000f;=0A= s->regs[reg] =3D val;=0A= aspeed_udc_update_irq(s);=0A= break;=0A= - case R_UDC_ISR:=0A= case R_UDC_EP_ACK_ISR:=0A= case R_UDC_EP_NAK_ISR:=0A= + val &=3D 0x0000000f;=0A= s->regs[reg] &=3D ~val;=0A= aspeed_udc_update_irq(s);=0A= break;=0A= -- =0A= 2.53.0=0A=