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Tue, 22 Sep 2026 03:16:31 -0700 (PDT) From: Yuchao Zhang To: Marc Zyngier Cc: Oliver Upton , Fuad Tabba , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yuchao Zhang Subject: Re: [PATCH v3 0/1] KVM: arm64: vgic: Drop last_lr_irq and serialize overflow EOI replay Date: Tue, 22 Sep 2026 18:16:23 +0800 Message-ID: <20260922101623.39468-1-ndaugoing@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <87bj9r4h9z.wl-maz@kernel.org> References: <87bj9r4h9z.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Marc, Thank you for the candid feedback and for cutting right to the heart of the problem with the 3-patch series on your branch. Your series is vastly simpler and elegant: 1. Only caching last_lr_irq when LRs are genuinely full eliminates the overhead for non-overflow exits. 2. Holding a proper reference on last_lr_irq and releasing it under ap_list_lock in vgic_prune_ap_list() cleanly addresses the lifetime hazard without introducing lock-order inversions during folding. 3. Halting the VM (kvm_arm_halt_guest) on remote GICR_CTLR.EnableLPIs=0 completely avoids cross-vCPU concurrency for an event that almost never happens in practice. As requested, I wrote a KVM arm64 selftest for this scenario: tools/testing/selftests/kvm/arm64/vgic_lpi_disable.c The test: - Configures an ITS with multiple LPIs targeting vCPU 0. - Keeps vCPU 0 in guest mode with EOImode=0 while injecting bursts of MSIs to force its List Registers to overflow into the ap_list. - Concurrently, vCPU 1 repeatedly toggles GICR_CTLR.EnableLPIs on vCPU 0's redistributor. Regarding testing: I currently no longer have access to KVM-capable hardware (my test setup is no longer available), so I cannot provide a Tested-by for your series. The race itself was originally identified through code inspection rather than a standalone reproducer, which is why I turned the theoretical scenario directly into this selftest. The selftest builds cleanly as part of the full arm64 kvm selftest suite, and its framework plumbing was smoke-tested under QEMU TCG, which by construction cannot exercise the race itself. I'd be grateful if you could give it a spin on your setup. The selftest patch is based on top of your kvm-arm64/vgic-last_lr_irq-fixes branch and has been sent in reply to this thread. Thanks, Yuchao