Re: [PATCH 2/2] arm64: dts: qcom: nord: add CoreSight debug nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] dts: sysfs naming collision due to duplicated DDR3 labels on DDR2 TPDMs
- [Low] dts: typo 'hpass' instead of 'lpass' in dummy source node name and label
- [Low] dts: inconsistent naming pattern for nsp0 static TPDM
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commit ecdfc6b26cc7775c5a0086623c2b989b0669a009
Author: Jie Gan <jie.gan@oss.qualcomm.com>

arm64: dts: qcom: nord: add CoreSight debug nodes

Add the CoreSight trace topology for the Qualcomm Nord SoC, including CTCU,
STM, TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF
sinks, and per-subsystem CTIs.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
[ ... ]
> +	hpass-stm {
> +		compatible = "arm,coresight-dummy-source";
> +		label = "hpass_stm";
> +		arm,static-trace-id = <25>;
> +
> +		out-ports {
> +			port {
> +				lpass_stm_out: endpoint {
> +					remote-endpoint = <&lpass_tn_in18>;

[Severity: Low]
Does this dummy source node name and label have a typo? It uses 'hpass', but
the endpoint connection and the commit message use 'lpass'.

[ ... ]
> +		tpdm@12410000 {
> +			compatible = "qcom,coresight-tpdm", "arm,primecell";
> +			reg = <0x0 0x12410000 0x0 0x1000>;
> +
> +			clocks = <&aoss_qmp>;
> +			clock-names = "apb_pclk";
> +			label = "tpdm_ddr3_llcc_2";

[Severity: Medium]
Can this sysfs label cause a naming collision? It incorrectly labels a DDR2
TPDM as DDR3. CoreSight drivers use this property to name devices in sysfs,
so it will collide with the actual DDR3 TPDM node at tpdm@12610000 during
boot.

[ ... ]
> +		tpdm@12411000 {
> +			compatible = "qcom,coresight-tpdm", "arm,primecell";
> +			reg = <0x0 0x12411000 0x0 0x1000>;
> +
> +			clocks = <&aoss_qmp>;
> +			clock-names = "apb_pclk";
> +			label = "tpdm_ddr3_llcc_3";

[Severity: Medium]
Similarly, will this label collide with the DDR3 node at tpdm@12611000? It
seems this should be labeled tpdm_ddr2_llcc_3.

[ ... ]
> +	tpdm-nsp0-cdsp-llm-2 {
> +		compatible = "qcom,coresight-static-tpdm";
> +		label = "tpdm_nsp0_cdsp_llm_2";

[Severity: Low]
This isn't a bug, but does this node's name and label deviate from the
established pattern? The static TPDM nodes for NSP1 through NSP3
consistently use the suffix 'llm2' (e.g., tpdm_nsp1_cdsp_llm2), whereas
this one uses 'llm_2'.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922100850.527109-1-shengchao.guo@oss.qualcomm.com?part=2