Re: [PATCH 2/3] drm/nouveau: pass HDMI GCP deep-color state through NVIF

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/nouveau: missing 30-bpp GCP configuration in nv50_hdmi_enable()
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commit a5a312ee20dba0d1f27e5316dc3d7c1c29070995
Author: Daniel Campos Ramos <Capitain_Jack@yahoo.com>
Subject: drm/nouveau: pass HDMI GCP deep-color state through NVIF

This commit adds HDMI GCP color depth and pixel packing phase configuration
to Nouveau to support 30, 36, and 48-bpp RGB links. It extends the NVIF
HDMI method to pass and cache these values for generation-specific writers.

> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
[ ... ]
> @@ -826,6 +827,19 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
>  	max_ac_packet -= 18; /* constant from tegra */
>  	max_ac_packet /= 32;
>  
> +	/* Match NVIDIA's 36-bpp GCP construction and extend the same HDMI
> +	 * color-depth encoding to 48-bpp.  48-bpp groups contain one pixel,
> +	 * so their last packing phase is phase 4 (zero).
> +	 */
> +	if (bpc == 16) {
> +		gcp_cd = 7;
> +	} else if (bpc == 12) {
> +		const u32 hbp = mode->crtc_hblank_end - mode->crtc_hsync_end;
> +
> +		gcp_cd = 6;
> +		gcp_pp = ((mode->crtc_hdisplay + hbp) & 1) ? 1 : 2;
> +	}
> +

[Severity: High]
Does this code omit the configuration for 30-bpp (10 bpc) HDMI streams?

If a monitor supports 30-bit deep color (DRM_EDID_HDMI_DC_30), asyh->or.bpc
is set to 10 in nv50_sor_atomic_enable() and passed here as bpc = 10. 
When bpc == 10, gcp_cd and gcp_pp are left as 0, which means "not indicated" 
and assumes a 24-bpp standard color depth.

Could this cause a corrupted or unreadable display output on 10-bit color 
monitors by violating the HDMI specification for Deep Color?

>  	if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
>  		const bool high_tmds_clock_ratio = mode->clock > 340000;
>  		u8 scdc;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260922192132.114546-1-Capitain_Jack@yahoo.com?part=2