From: sashiko-bot@kernel.org
To: "Ali Rouhi" <arouhi@sitime.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v10 08/14] dpll: sit9531x: add support to get and set frequency on pins
Date: Tue, 22 Sep 2026 20:11:44 +0000 [thread overview]
Message-ID: <20260922201145.142541F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260921201108.42676-9-arouhi@sitime.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dpll: sit9531x: unconditional NVM commit on I2C write failure corrupts hardware state
--
commit 6cf2285c5820470a1c24c7b915f31d2eb06496d4
Author: Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>
dpll: sit9531x: add support to get and set frequency on pins
This commit introduces frequency getting and setting for the sit9531x
DPLL driver. It handles both input frequency reporting from firmware
and output frequency configuration by writing new dividers to the chip.
> diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c
> --- a/drivers/dpll/sit9531x/core.c
> +++ b/drivers/dpll/sit9531x/core.c
[ ... ]
> +int sit9531x_output_freq_set(struct sit9531x_dev *sitdev, u8 out_idx,
> + u8 pll_idx, u64 frequency)
> +{
> + u64 fvco, divo;
> + int rc, ret;
> +
> + lockdep_assert_held(&sitdev->multiop_lock);
> +
> + rc = sit9531x_output_divo_calc(sitdev, out_idx, pll_idx, frequency,
> + &fvco, &divo);
> + if (rc)
> + return rc;
> +
> + rc = sit9531x_prg_enter(sitdev);
> + if (rc)
> + return rc;
> +
> + rc = sit9531x_output_divo_write(sitdev, out_idx, divo);
> + /*
> + * Step 4: NVM update + loop lock. Always run prg_commit() so the chip
> + * leaves the PRG_CMD state with the output loops re-locked, even when a
> + * write above failed; keep the first error to return. It also carries
> + * the required post-lock settling sleep.
> + */
> + ret = sit9531x_prg_commit(sitdev);
[Severity: High]
Will this persist corrupted values to non-volatile memory if an I2C bus error
occurs during the divider write?
If a multi-byte I2C write for the output divider fails in
sit9531x_output_divo_write() or its rollback sequence, the error path
unconditionally calls sit9531x_prg_commit() to re-lock the loops.
However, looking at sit9531x_prg_commit(), it unconditionally issues the
SIT9531X_UPDATE_NVM command:
static int sit9531x_prg_commit(struct sit9531x_dev *sitdev)
{
int rc, rc2 = 0, rc3;
u8 attempt;
rc = sit9531x_write_u8(sitdev, SIT9531X_REG_PRG_DIR_GEN,
SIT9531X_UPDATE_NVM);
...
}
This persists the partially-written divider values into NVM, which
could permanently break the device's default boot configuration. Should this
path call sit9531x_prg_abort() instead when sit9531x_output_divo_write()
returns an error, so the loops can be safely re-locked without issuing an
NVM update?
> + if (ret && !rc)
> + rc = ret;
> + if (rc)
> + return rc;
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260921201108.42676-1-arouhi@sitime.com?part=8
next prev parent reply other threads:[~2026-09-22 20:11 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 20:11 [PATCH v10 00/14] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 01/14] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 02/14] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 03/14] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 04/14] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 05/14] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 06/14] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 07/14] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 08/14] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-09-22 20:11 ` sashiko-bot [this message]
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 09/14] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 11/14] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 10/14] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 12/14] dpll: sit9531x: add support to get fractional frequency offset Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 13/14] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 14/14] dpll: sit9531x: allow the device tree to override two board facts Ali Rouhi
2026-09-22 20:11 ` sashiko-bot
2026-09-26 2:34 ` Jakub Kicinski
2026-09-28 23:29 ` [PATCH v10 00/14] dpll: add SiTime SiT9531x DPLL clock driver Jakub Kicinski
2026-09-29 0:38 ` Ali Rouhi
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