Re: [PATCH 3/4] arm64: dts: qcom: Introduce Hawi SoC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dt: pcie iommu-map property missing mask cell
--

commit b9bce85781ff89249270f3214ceed073984ef78e
Author: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>

arm64: dts: qcom: Introduce Hawi SoC

This commit introduces the device tree definition for the Qualcomm Hawi SoC.
It adds a large number of nodes including CPUs, interrupts, timers, reserved
memory, interconnects, SMMU, PCIe, USB, thermal zones, and remoteprocs.

> diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
> new file mode 100644
> index 0000000000000..c7ae8133b9cdc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/hawi.dtsi

[ ... ]

> @@ -2957,8 +2957,8 @@
>  
>  			operating-points-v2 = <&pcie0_opp_table>;
>  
> +			iommu-map = <0 &apps_smmu 0x1000 0x1>,
> +				    <0x100 &apps_smmu 0x1001 0x1>;

[Severity: High]
Are we missing a mask cell for the SMMU specifier in this iommu-map property?

The apps_smmu node defines #iommu-cells = <2>, which means the iommu-map
array requires 5 cells per tuple (rid-base, phandle, iommu-base-high, 
iommu-base-low, length). Providing only 4 cells per tuple can cause the
parser to misalign the tuples, treating the length as part of the iommu-base
mask and stealing the next tuple's rid-base for the length. This completely
breaks parsing of the IOMMU specifier and results in broken PCIe DMA
translation.

> +
> +			interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>,

[ ... ]

> @@ -3139,8 +3139,8 @@
>  
>  			operating-points-v2 = <&pcie1_opp_table>;
>  
> +			iommu-map = <0 &apps_smmu 0x1080 0x1>,
> +				    <0x100 &apps_smmu 0x1081 0x1>;

[Severity: High]
Is this iommu-map array similarly missing a mask cell for the SMMU
specifier?

As with the pcie0 node above, providing 4 cells per tuple when 5 are
expected can cause parsing issues that break the IOMMU specifier.

> +
> +			interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 106 IRQ_TYPE_LEVEL_HIGH>,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260923-hawi-dt-post-v1-0-e41473b6298b@oss.qualcomm.com?part=3