diff for duplicates of <202609230734.R1jtbjb4-lkp@intel.com> diff --git a/a/1.txt b/N1/1.txt index 08f93ef..f9de975 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,15 @@ +BCC: lkp@intel.com +CC: oe-kbuild-all@lists.linux.dev +TO: bui duc phuc <phucduc.bui@gmail.com> +CC: Jakub Kicinski <kuba@kernel.org> +CC: Simon Horman <horms@kernel.org> +CC: Suraj Gupta <suraj.gupta2@amd.com> + tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: a8c591ed6b672915e0be57843f943a2a723aff40 commit: bb2b71024976a39ed57d66bad8f9ca7e93bc3f33 [4776/8910] net: xilinx: axienet: Fix IRQ error handling +:::::: branch date: 16 hours ago +:::::: commit date: 11 days ago config: i386-randconfig-2200-20260923 (https://download.01.org/0day-ci/archive/20260923/202609230734.R1jtbjb4-lkp@intel.com/config) compiler: gcc-12 (Debian 12.4.0-5) 12.4.0 smatch: v0.5.0-9187-g5189e3fb @@ -13,9 +22,170 @@ the same patch/commit), kindly add following tags smatch warnings: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2974 axienet_probe() warn: platform_get_irq() does not return zero +drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2974 axienet_probe() warn: platform_get_irq() does not return zero vim +2974 drivers/net/ethernet/xilinx/xilinx_axienet_main.c +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2782 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2783 /** +2be586205ca2b81 Srikanth Thokala 2015-05-05 2784 * axienet_probe - Axi Ethernet probe function. +95219aa538e11d5 Srikanth Thokala 2015-05-05 2785 * @pdev: Pointer to platform device structure. +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2786 * +b0d081c524b46c2 Michal Simek 2015-05-05 2787 * Return: 0, on success +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2788 * Non-zero error value on failure. +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2789 * +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2790 * This is the probe routine for Axi Ethernet driver. This is called before +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2791 * any other driver routines are invoked. It allocates and sets up the Ethernet +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2792 * device. Parses through device tree and populates fields of +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2793 * axienet_local. It registers the Ethernet device. +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2794 */ +2be586205ca2b81 Srikanth Thokala 2015-05-05 2795 static int axienet_probe(struct platform_device *pdev) +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2796 { +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2797 int ret; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2798 struct device_node *np; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2799 struct axienet_local *lp; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2800 struct net_device *ndev; +28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2801 struct resource *ethres; +83216e3988cd196 Michael Walle 2021-04-12 2802 u8 mac_addr[ETH_ALEN]; +5fff0151b3244dc Andre Przywara 2020-03-24 2803 int addr_width = 32; +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2804 u32 value; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2805 +808d077f5b53806 Sean Anderson 2026-01-17 2806 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp)); +41de8d4cff21a2e Joe Perches 2012-01-29 2807 if (!ndev) +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2808 return -ENOMEM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2809 +95219aa538e11d5 Srikanth Thokala 2015-05-05 2810 platform_set_drvdata(pdev, ndev); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2811 +95219aa538e11d5 Srikanth Thokala 2015-05-05 2812 SET_NETDEV_DEV(ndev, &pdev->dev); +28e24c62ab3062e Eric Dumazet 2013-12-02 2813 ndev->features = NETIF_F_SG; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2814 +d894be57ca92c8a Jarod Wilson 2016-10-20 2815 /* MTU range: 64 - 9000 */ +d894be57ca92c8a Jarod Wilson 2016-10-20 2816 ndev->min_mtu = 64; +d894be57ca92c8a Jarod Wilson 2016-10-20 2817 ndev->max_mtu = XAE_JUMBO_MTU; +d894be57ca92c8a Jarod Wilson 2016-10-20 2818 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2819 lp = netdev_priv(ndev); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2820 lp->ndev = ndev; +95219aa538e11d5 Srikanth Thokala 2015-05-05 2821 lp->dev = &pdev->dev; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2822 lp->options = XAE_OPTION_DEFAULTS; +8b09ca823ffb4ee Robert Hancock 2019-06-06 2823 lp->rx_bd_num = RX_BD_NUM_DEFAULT; +8b09ca823ffb4ee Robert Hancock 2019-06-06 2824 lp->tx_bd_num = TX_BD_NUM_DEFAULT; +57baf8cc70ea4cf Robert Hancock 2021-02-12 2825 +cb45a8bf4693965 Robert Hancock 2022-08-29 2826 u64_stats_init(&lp->rx_stat_sync); +cb45a8bf4693965 Robert Hancock 2022-08-29 2827 u64_stats_init(&lp->tx_stat_sync); +cb45a8bf4693965 Robert Hancock 2022-08-29 2828 +76abb5d675c49ba Sean Anderson 2024-08-20 2829 mutex_init(&lp->stats_lock); +76abb5d675c49ba Sean Anderson 2024-08-20 2830 seqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock); +76abb5d675c49ba Sean Anderson 2024-08-20 2831 INIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats); +76abb5d675c49ba Sean Anderson 2024-08-20 2832 +808d077f5b53806 Sean Anderson 2026-01-17 2833 lp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev, +808d077f5b53806 Sean Anderson 2026-01-17 2834 "s_axi_lite_clk"); +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2835 if (!lp->axi_clk) { +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2836 /* For backward compatibility, if named AXI clock is not present, +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2837 * treat the first clock specified as the AXI clock. +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2838 */ +808d077f5b53806 Sean Anderson 2026-01-17 2839 lp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); +57baf8cc70ea4cf Robert Hancock 2021-02-12 2840 } +808d077f5b53806 Sean Anderson 2026-01-17 2841 if (IS_ERR(lp->axi_clk)) +808d077f5b53806 Sean Anderson 2026-01-17 2842 return dev_err_probe(&pdev->dev, PTR_ERR(lp->axi_clk), +808d077f5b53806 Sean Anderson 2026-01-17 2843 "could not get AXI clock\n"); +57baf8cc70ea4cf Robert Hancock 2021-02-12 2844 +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2845 lp->misc_clks[0].id = "axis_clk"; +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2846 lp->misc_clks[1].id = "ref_clk"; +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2847 lp->misc_clks[2].id = "mgt_clk"; +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2848 +808d077f5b53806 Sean Anderson 2026-01-17 2849 ret = devm_clk_bulk_get_optional_enable(&pdev->dev, XAE_NUM_MISC_CLOCKS, +808d077f5b53806 Sean Anderson 2026-01-17 2850 lp->misc_clks); +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2851 if (ret) +808d077f5b53806 Sean Anderson 2026-01-17 2852 return dev_err_probe(&pdev->dev, ret, +808d077f5b53806 Sean Anderson 2026-01-17 2853 "could not get/enable misc. clocks\n"); +b11bfb9a19f9d79 Robert Hancock 2021-03-25 2854 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2855 /* Map device registers */ +47651c51c02fc49 Yang Yingliang 2021-06-10 2856 lp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ðres); +808d077f5b53806 Sean Anderson 2026-01-17 2857 if (IS_ERR(lp->regs)) +808d077f5b53806 Sean Anderson 2026-01-17 2858 return PTR_ERR(lp->regs); +7fa0043d5c74c6e Robert Hancock 2019-06-11 2859 lp->regs_start = ethres->start; +46aa27df8853214 Srikanth Thokala 2015-05-05 2860 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2861 /* Setup checksum offload, but default to off if not specified */ +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2862 lp->features = 0; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2863 +76abb5d675c49ba Sean Anderson 2024-08-20 2864 if (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_STATS) +76abb5d675c49ba Sean Anderson 2024-08-20 2865 lp->features |= XAE_FEATURE_STATS; +76abb5d675c49ba Sean Anderson 2024-08-20 2866 +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2867 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value); +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2868 if (!ret) { +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2869 switch (value) { +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2870 case 1: +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2871 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM; +dd28f4c0e81f42b Sean Anderson 2024-09-09 2872 /* Can checksum any contiguous range */ +dd28f4c0e81f42b Sean Anderson 2024-09-09 2873 ndev->features |= NETIF_F_HW_CSUM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2874 break; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2875 case 2: +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2876 lp->features |= XAE_FEATURE_FULL_TX_CSUM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2877 /* Can checksum TCP/UDP over IPv4. */ +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2878 ndev->features |= NETIF_F_IP_CSUM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2879 break; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2880 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2881 } +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2882 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value); +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2883 if (!ret) { +8495659bf93c8e2 Srikanth Thokala 2015-05-05 2884 switch (value) { +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2885 case 1: +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2886 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM; +06c069ff2f7013f Sean Anderson 2024-09-09 2887 ndev->features |= NETIF_F_RXCSUM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2888 break; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2889 case 2: +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2890 lp->features |= XAE_FEATURE_FULL_RX_CSUM; +06c069ff2f7013f Sean Anderson 2024-09-09 2891 ndev->features |= NETIF_F_RXCSUM; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2892 break; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2893 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2894 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2895 /* For supporting jumbo frames, the Axi Ethernet hardware must have +f080a8c35d8932d Srikanth Thokala 2015-05-05 2896 * a larger Rx/Tx Memory. Typically, the size must be large so that +f080a8c35d8932d Srikanth Thokala 2015-05-05 2897 * we can enable jumbo option and start supporting jumbo frames. +f080a8c35d8932d Srikanth Thokala 2015-05-05 2898 * Here we check for memory allocated for Rx/Tx in the hardware from +f080a8c35d8932d Srikanth Thokala 2015-05-05 2899 * the device-tree and accordingly set flags. +f080a8c35d8932d Srikanth Thokala 2015-05-05 2900 */ +34b270e7893f4a1 Suraj Gupta 2026-08-06 2901 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); +34b270e7893f4a1 Suraj Gupta 2026-08-06 2902 if (ret) +34b270e7893f4a1 Suraj Gupta 2026-08-06 2903 return dev_err_probe(&pdev->dev, ret, +34b270e7893f4a1 Suraj Gupta 2026-08-06 2904 "failed to read xlnx,rxmem property\n"); +ee06b1728b95643 Alvaro G. M 2017-07-17 2905 +6c8f06bb2e5147b Robert Hancock 2021-02-12 2906 lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node, +6c8f06bb2e5147b Robert Hancock 2021-02-12 2907 "xlnx,switch-x-sgmii"); +6c8f06bb2e5147b Robert Hancock 2021-02-12 2908 +ee06b1728b95643 Alvaro G. M 2017-07-17 2909 /* Start with the proprietary, and broken phy_type */ +ee06b1728b95643 Alvaro G. M 2017-07-17 2910 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); +ee06b1728b95643 Alvaro G. M 2017-07-17 2911 if (!ret) { +ee06b1728b95643 Alvaro G. M 2017-07-17 2912 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode"); +ee06b1728b95643 Alvaro G. M 2017-07-17 2913 switch (value) { +ee06b1728b95643 Alvaro G. M 2017-07-17 2914 case XAE_PHY_TYPE_MII: +ee06b1728b95643 Alvaro G. M 2017-07-17 2915 lp->phy_mode = PHY_INTERFACE_MODE_MII; +ee06b1728b95643 Alvaro G. M 2017-07-17 2916 break; +ee06b1728b95643 Alvaro G. M 2017-07-17 2917 case XAE_PHY_TYPE_GMII: +ee06b1728b95643 Alvaro G. M 2017-07-17 2918 lp->phy_mode = PHY_INTERFACE_MODE_GMII; +ee06b1728b95643 Alvaro G. M 2017-07-17 2919 break; +ee06b1728b95643 Alvaro G. M 2017-07-17 2920 case XAE_PHY_TYPE_RGMII_2_0: +ee06b1728b95643 Alvaro G. M 2017-07-17 2921 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID; +ee06b1728b95643 Alvaro G. M 2017-07-17 2922 break; +ee06b1728b95643 Alvaro G. M 2017-07-17 2923 case XAE_PHY_TYPE_SGMII: +ee06b1728b95643 Alvaro G. M 2017-07-17 2924 lp->phy_mode = PHY_INTERFACE_MODE_SGMII; +ee06b1728b95643 Alvaro G. M 2017-07-17 2925 break; +ee06b1728b95643 Alvaro G. M 2017-07-17 2926 case XAE_PHY_TYPE_1000BASE_X: +ee06b1728b95643 Alvaro G. M 2017-07-17 2927 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX; +ee06b1728b95643 Alvaro G. M 2017-07-17 2928 break; +ee06b1728b95643 Alvaro G. M 2017-07-17 2929 default: +808d077f5b53806 Sean Anderson 2026-01-17 2930 return -EINVAL; +ee06b1728b95643 Alvaro G. M 2017-07-17 2931 } +ee06b1728b95643 Alvaro G. M 2017-07-17 2932 } else { +0c65b2b90d13c1d Andrew Lunn 2019-11-04 2933 ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode); +0c65b2b90d13c1d Andrew Lunn 2019-11-04 2934 if (ret) +808d077f5b53806 Sean Anderson 2026-01-17 2935 return ret; +ee06b1728b95643 Alvaro G. M 2017-07-17 2936 } +6c8f06bb2e5147b Robert Hancock 2021-02-12 2937 if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII && +6c8f06bb2e5147b Robert Hancock 2021-02-12 2938 lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) { +6c8f06bb2e5147b Robert Hancock 2021-02-12 2939 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n"); +808d077f5b53806 Sean Anderson 2026-01-17 2940 return -EINVAL; +6c8f06bb2e5147b Robert Hancock 2021-02-12 2941 } 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2942 5fe164fb0e6e31d Rob Herring (Arm 2024-07-31 2943) if (!of_property_present(pdev->dev.of_node, "dmas")) { 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2944 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ @@ -41,10 +211,7 @@ d6349e3e14c7f7b Andre Przywara 2020-03-24 2962 lp->eth_irq = plat 28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2964 /* Check for these resources directly on the Ethernet node. */ 47651c51c02fc49 Yang Yingliang 2021-06-10 2965 lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2966 lp->rx_irq = platform_get_irq(pdev, 1); - ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2967 lp->tx_irq = platform_get_irq(pdev, 0); - ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - d6349e3e14c7f7b Andre Przywara 2020-03-24 2968 lp->eth_irq = platform_get_irq_optional(pdev, 2); 28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2969 } fcc028c106e5750 Krzysztof Kozlowski 2015-07-09 2970 if (IS_ERR(lp->dma_regs)) { @@ -52,13 +219,186 @@ fcc028c106e5750 Krzysztof Kozlowski 2015-07-09 2970 if (IS_ERR(lp->dma_ 808d077f5b53806 Sean Anderson 2026-01-17 2972 return PTR_ERR(lp->dma_regs); 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2973 } bb2b71024976a39 bui duc phuc 2026-09-09 @2974 if (!lp->rx_irq || !lp->tx_irq) { - -These should be checks for negative instead of zero. - 95219aa538e11d5 Srikanth Thokala 2015-05-05 2975 dev_err(&pdev->dev, "could not determine irqs\n"); bb2b71024976a39 bui duc phuc 2026-09-09 2976 return -EINVAL; 8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2977 } bb2b71024976a39 bui duc phuc 2026-09-09 2978 if (lp->rx_irq < 0) +bb2b71024976a39 bui duc phuc 2026-09-09 2979 return lp->rx_irq; +bb2b71024976a39 bui duc phuc 2026-09-09 2980 if (lp->tx_irq < 0) +bb2b71024976a39 bui duc phuc 2026-09-09 2981 return lp->tx_irq; +90ab44517ee1f9e bui duc phuc 2026-09-09 2982 if (lp->eth_irq < 0 && lp->eth_irq != -ENXIO) +90ab44517ee1f9e bui duc phuc 2026-09-09 2983 return lp->eth_irq; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2984 +f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2985 /* Reset core now that clocks are enabled, prior to accessing MDIO */ +f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2986 ret = __axienet_device_reset(lp); +f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2987 if (ret) +808d077f5b53806 Sean Anderson 2026-01-17 2988 return ret; +f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2989 +f735c40ed93ccae Andre Przywara 2020-03-24 2990 /* Autodetect the need for 64-bit DMA pointers. +f735c40ed93ccae Andre Przywara 2020-03-24 2991 * When the IP is configured for a bus width bigger than 32 bits, +f735c40ed93ccae Andre Przywara 2020-03-24 2992 * writing the MSB registers is mandatory, even if they are all 0. +f735c40ed93ccae Andre Przywara 2020-03-24 2993 * We can detect this case by writing all 1's to one such register +f735c40ed93ccae Andre Przywara 2020-03-24 2994 * and see if that sticks: when the IP is configured for 32 bits +f735c40ed93ccae Andre Przywara 2020-03-24 2995 * only, those registers are RES0. +f735c40ed93ccae Andre Przywara 2020-03-24 2996 * Those MSB registers were introduced in IP v7.1, which we check first. +f735c40ed93ccae Andre Przywara 2020-03-24 2997 */ +f735c40ed93ccae Andre Przywara 2020-03-24 2998 if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { +f735c40ed93ccae Andre Przywara 2020-03-24 2999 void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; +f735c40ed93ccae Andre Przywara 2020-03-24 3000 +f735c40ed93ccae Andre Przywara 2020-03-24 3001 iowrite32(0x0, desc); +f735c40ed93ccae Andre Przywara 2020-03-24 3002 if (ioread32(desc) == 0) { /* sanity check */ +f735c40ed93ccae Andre Przywara 2020-03-24 3003 iowrite32(0xffffffff, desc); +f735c40ed93ccae Andre Przywara 2020-03-24 3004 if (ioread32(desc) > 0) { +f735c40ed93ccae Andre Przywara 2020-03-24 3005 lp->features |= XAE_FEATURE_DMA_64BIT; +5fff0151b3244dc Andre Przywara 2020-03-24 3006 addr_width = 64; +f735c40ed93ccae Andre Przywara 2020-03-24 3007 dev_info(&pdev->dev, +f735c40ed93ccae Andre Przywara 2020-03-24 3008 "autodetected 64-bit DMA range\n"); +f735c40ed93ccae Andre Przywara 2020-03-24 3009 } +f735c40ed93ccae Andre Przywara 2020-03-24 3010 iowrite32(0x0, desc); +f735c40ed93ccae Andre Przywara 2020-03-24 3011 } +f735c40ed93ccae Andre Przywara 2020-03-24 3012 } +00be43a74ca2622 Andy Chiu 2022-06-13 3013 if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { +61fde5110ee9f1f Colin Ian King 2025-04-18 3014 dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit architecture\n"); +808d077f5b53806 Sean Anderson 2026-01-17 3015 return -EINVAL; +00be43a74ca2622 Andy Chiu 2022-06-13 3016 } +f735c40ed93ccae Andre Przywara 2020-03-24 3017 +5fff0151b3244dc Andre Przywara 2020-03-24 3018 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); +5fff0151b3244dc Andre Przywara 2020-03-24 3019 if (ret) { +5fff0151b3244dc Andre Przywara 2020-03-24 3020 dev_err(&pdev->dev, "No suitable DMA available\n"); +808d077f5b53806 Sean Anderson 2026-01-17 3021 return ret; +5fff0151b3244dc Andre Przywara 2020-03-24 3022 } +6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3023 netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); +6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3024 netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3025 } else { +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3026 struct xilinx_vdma_config cfg; +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3027 struct dma_chan *tx_chan; +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3028 +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3029 lp->eth_irq = platform_get_irq_optional(pdev, 0); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3030 if (lp->eth_irq < 0 && lp->eth_irq != -ENXIO) { +808d077f5b53806 Sean Anderson 2026-01-17 3031 return lp->eth_irq; +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3032 } +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3033 tx_chan = dma_request_chan(lp->dev, "tx_chan0"); +808d077f5b53806 Sean Anderson 2026-01-17 3034 if (IS_ERR(tx_chan)) +808d077f5b53806 Sean Anderson 2026-01-17 3035 return dev_err_probe(lp->dev, PTR_ERR(tx_chan), +808d077f5b53806 Sean Anderson 2026-01-17 3036 "No Ethernet DMA (TX) channel found\n"); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3037 +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3038 cfg.reset = 1; +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3039 /* As name says VDMA but it has support for DMA channel reset */ +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3040 ret = xilinx_vdma_channel_set_config(tx_chan, &cfg); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3041 if (ret < 0) { +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3042 dev_err(&pdev->dev, "Reset channel failed\n"); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3043 dma_release_channel(tx_chan); +808d077f5b53806 Sean Anderson 2026-01-17 3044 return ret; +6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3045 } +5fff0151b3244dc Andre Przywara 2020-03-24 3046 +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3047 dma_release_channel(tx_chan); +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3048 lp->use_dmaengine = 1; +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3049 } +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3050 +c1c3d01e3a9038d Suraj Gupta 2026-06-01 3051 if (lp->use_dmaengine) { +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3052 ndev->netdev_ops = &axienet_netdev_dmaengine_ops; +c1c3d01e3a9038d Suraj Gupta 2026-06-01 3053 ndev->ethtool_ops = &axienet_ethtool_dmaengine_ops; +c1c3d01e3a9038d Suraj Gupta 2026-06-01 3054 } else { +6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3055 ndev->netdev_ops = &axienet_netdev_ops; +c1c3d01e3a9038d Suraj Gupta 2026-06-01 3056 ndev->ethtool_ops = &axienet_ethtool_ops; +c1c3d01e3a9038d Suraj Gupta 2026-06-01 3057 } +522856cefaf09d1 Robert Hancock 2019-06-06 3058 /* Check for Ethernet core IRQ (optional) */ +2d2f18d49221846 bui duc phuc 2026-09-09 3059 if (lp->eth_irq < 0) +522856cefaf09d1 Robert Hancock 2019-06-06 3060 dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); +522856cefaf09d1 Robert Hancock 2019-06-06 3061 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3062 /* Retrieve the MAC address */ +83216e3988cd196 Michael Walle 2021-04-12 3063 ret = of_get_mac_address(pdev->dev.of_node, mac_addr); +83216e3988cd196 Michael Walle 2021-04-12 3064 if (!ret) { +da90e38003e2f05 Tobias Klauser 2016-12-07 3065 axienet_set_mac_address(ndev, mac_addr); +83216e3988cd196 Michael Walle 2021-04-12 3066 } else { +83216e3988cd196 Michael Walle 2021-04-12 3067 dev_warn(&pdev->dev, "could not find MAC address property: %d\n", +83216e3988cd196 Michael Walle 2021-04-12 3068 ret); +83216e3988cd196 Michael Walle 2021-04-12 3069 axienet_set_mac_address(ndev, NULL); +83216e3988cd196 Michael Walle 2021-04-12 3070 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3071 +d048c717df33baf Sean Anderson 2025-02-06 3072 spin_lock_init(&lp->rx_cr_lock); +d048c717df33baf Sean Anderson 2025-02-06 3073 spin_lock_init(&lp->tx_cr_lock); +e1d27d29dbe5139 Sean Anderson 2025-02-06 3074 INIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work); +e1d27d29dbe5139 Sean Anderson 2025-02-06 3075 lp->rx_dim_enabled = true; +e1d27d29dbe5139 Sean Anderson 2025-02-06 3076 lp->rx_dim.profile_ix = 1; +e1d27d29dbe5139 Sean Anderson 2025-02-06 3077 lp->rx_dma_cr = axienet_calc_cr(lp, axienet_dim_coalesce_count_rx(lp), +eb80520e8a5be67 Sean Anderson 2025-02-06 3078 XAXIDMA_DFT_RX_USEC); +eb80520e8a5be67 Sean Anderson 2025-02-06 3079 lp->tx_dma_cr = axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD, +eb80520e8a5be67 Sean Anderson 2025-02-06 3080 XAXIDMA_DFT_TX_USEC); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3081 +09a0354cadec267 Robert Hancock 2019-06-06 3082 ret = axienet_mdio_setup(lp); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3083 if (ret) +09a0354cadec267 Robert Hancock 2019-06-06 3084 dev_warn(&pdev->dev, +09a0354cadec267 Robert Hancock 2019-06-06 3085 "error registering MDIO bus: %d\n", ret); +d1c4f93e3f0a023 Andy Chiu 2022-04-05 3086 +1a02556086fc0eb Robert Hancock 2020-10-28 3087 if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII || +1a02556086fc0eb Robert Hancock 2020-10-28 3088 lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) { +19c7a43912c61a3 Andy Chiu 2022-04-05 3089 np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0); +19c7a43912c61a3 Andy Chiu 2022-04-05 3090 if (!np) { +19c7a43912c61a3 Andy Chiu 2022-04-05 3091 /* Deprecated: Always use "pcs-handle" for pcs_phy. +19c7a43912c61a3 Andy Chiu 2022-04-05 3092 * Falling back to "phy-handle" here is only for +19c7a43912c61a3 Andy Chiu 2022-04-05 3093 * backward compatibility with old device trees. +19c7a43912c61a3 Andy Chiu 2022-04-05 3094 */ +ab3a5d4c6081dbc Andy Chiu 2022-04-05 3095 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); +19c7a43912c61a3 Andy Chiu 2022-04-05 3096 } +ab3a5d4c6081dbc Andy Chiu 2022-04-05 3097 if (!np) { +19c7a43912c61a3 Andy Chiu 2022-04-05 3098 dev_err(&pdev->dev, "pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\n"); +1a02556086fc0eb Robert Hancock 2020-10-28 3099 ret = -EINVAL; +59cd4f19267a0aa Robert Hancock 2021-03-11 3100 goto cleanup_mdio; +1a02556086fc0eb Robert Hancock 2020-10-28 3101 } +ab3a5d4c6081dbc Andy Chiu 2022-04-05 3102 lp->pcs_phy = of_mdio_find_device(np); +1a02556086fc0eb Robert Hancock 2020-10-28 3103 if (!lp->pcs_phy) { +1a02556086fc0eb Robert Hancock 2020-10-28 3104 ret = -EPROBE_DEFER; +ab3a5d4c6081dbc Andy Chiu 2022-04-05 3105 of_node_put(np); +59cd4f19267a0aa Robert Hancock 2021-03-11 3106 goto cleanup_mdio; +1a02556086fc0eb Robert Hancock 2020-10-28 3107 } +ab3a5d4c6081dbc Andy Chiu 2022-04-05 3108 of_node_put(np); +7a86be6a5135eaa Russell King (Oracle 2022-01-25 3109) lp->pcs.ops = &axienet_pcs_ops; +7a86be6a5135eaa Russell King (Oracle 2022-01-25 3110) lp->pcs.poll = true; +1a02556086fc0eb Robert Hancock 2020-10-28 3111 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3112 +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3113 lp->phylink_config.dev = &ndev->dev; +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3114 lp->phylink_config.type = PHYLINK_NETDEV; +a370295367b5566 Nick Hu 2025-02-17 3115 lp->phylink_config.mac_managed_pm = true; +72a47e1aaf2e05e Russell King (Oracle 2021-11-16 3116) lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | +72a47e1aaf2e05e Russell King (Oracle 2021-11-16 3117) MAC_10FD | MAC_100FD | MAC_1000FD; +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3118 +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3119) __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3120) if (lp->switch_x_sgmii) { +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3121) __set_bit(PHY_INTERFACE_MODE_1000BASEX, +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3122) lp->phylink_config.supported_interfaces); +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3123) __set_bit(PHY_INTERFACE_MODE_SGMII, +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3124) lp->phylink_config.supported_interfaces); +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3125) } +136a3fa28a9f562 Russell King (Oracle 2021-11-16 3126) +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3127 lp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode, +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3128 lp->phy_mode, +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3129 &axienet_phylink_ops); +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3130 if (IS_ERR(lp->phylink)) { +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3131 ret = PTR_ERR(lp->phylink); +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3132 dev_err(&pdev->dev, "phylink_create error (%i)\n", ret); +59cd4f19267a0aa Robert Hancock 2021-03-11 3133 goto cleanup_mdio; +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3134 } +f5203a3d9b25fa2 Robert Hancock 2019-06-06 3135 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3136 ret = register_netdev(lp->ndev); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3137 if (ret) { +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3138 dev_err(lp->dev, "register_netdev() error (%i)\n", ret); +59cd4f19267a0aa Robert Hancock 2021-03-11 3139 goto cleanup_phylink; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3140 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3141 +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3142 return 0; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3143 +59cd4f19267a0aa Robert Hancock 2021-03-11 3144 cleanup_phylink: +59cd4f19267a0aa Robert Hancock 2021-03-11 3145 phylink_destroy(lp->phylink); +59cd4f19267a0aa Robert Hancock 2021-03-11 3146 +59cd4f19267a0aa Robert Hancock 2021-03-11 3147 cleanup_mdio: +59cd4f19267a0aa Robert Hancock 2021-03-11 3148 if (lp->pcs_phy) +59cd4f19267a0aa Robert Hancock 2021-03-11 3149 put_device(&lp->pcs_phy->dev); +59cd4f19267a0aa Robert Hancock 2021-03-11 3150 if (lp->mii_bus) +59cd4f19267a0aa Robert Hancock 2021-03-11 3151 axienet_mdio_teardown(lp); +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3152 return ret; +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3153 } +8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3154 -- 0-DAY CI Kernel Test Service diff --git a/a/content_digest b/N1/content_digest index 9d2007c..b174340 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,23 @@ - "From\0Dan Carpenter <error27@gmail.com>\0" + "From\0kernel test robot <lkp@intel.com>\0" "Subject\0[linux-next:master 4776/8910] drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2974 axienet_probe() warn: platform_get_irq() does not return zero\0" - "Date\0Wed, 23 Sep 2026 09:40:58 +0300\0" - "To\0oe-kbuild@lists.linux.dev" - " bui duc phuc <phucduc.bui@gmail.com>\0" + "Date\0Wed, 23 Sep 2026 07:22:57 +0200\0" + "To\0oe-kbuild@lists.linux.dev\0" "Cc\0lkp@intel.com" - oe-kbuild-all@lists.linux.dev - Jakub Kicinski <kuba@kernel.org> - Simon Horman <horms@kernel.org> - " Suraj Gupta <suraj.gupta2@amd.com>\0" + " Dan Carpenter <error27@gmail.com>\0" "\00:1\0" "b\0" + "BCC: lkp@intel.com\n" + "CC: oe-kbuild-all@lists.linux.dev\n" + "TO: bui duc phuc <phucduc.bui@gmail.com>\n" + "CC: Jakub Kicinski <kuba@kernel.org>\n" + "CC: Simon Horman <horms@kernel.org>\n" + "CC: Suraj Gupta <suraj.gupta2@amd.com>\n" + "\n" "tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master\n" "head: a8c591ed6b672915e0be57843f943a2a723aff40\n" "commit: bb2b71024976a39ed57d66bad8f9ca7e93bc3f33 [4776/8910] net: xilinx: axienet: Fix IRQ error handling\n" + ":::::: branch date: 16 hours ago\n" + ":::::: commit date: 11 days ago\n" "config: i386-randconfig-2200-20260923 (https://download.01.org/0day-ci/archive/20260923/202609230734.R1jtbjb4-lkp@intel.com/config)\n" "compiler: gcc-12 (Debian 12.4.0-5) 12.4.0\n" "smatch: v0.5.0-9187-g5189e3fb\n" @@ -25,9 +30,170 @@ "\n" "smatch warnings:\n" "drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2974 axienet_probe() warn: platform_get_irq() does not return zero\n" + "drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2974 axienet_probe() warn: platform_get_irq() does not return zero\n" "\n" "vim +2974 drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n" "\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2782 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2783 /**\n" + "2be586205ca2b81 Srikanth Thokala 2015-05-05 2784 * axienet_probe - Axi Ethernet probe function.\n" + "95219aa538e11d5 Srikanth Thokala 2015-05-05 2785 * @pdev:\tPointer to platform device structure.\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2786 *\n" + "b0d081c524b46c2 Michal Simek 2015-05-05 2787 * Return: 0, on success\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2788 *\t Non-zero error value on failure.\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2789 *\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2790 * This is the probe routine for Axi Ethernet driver. This is called before\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2791 * any other driver routines are invoked. It allocates and sets up the Ethernet\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2792 * device. Parses through device tree and populates fields of\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2793 * axienet_local. It registers the Ethernet device.\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2794 */\n" + "2be586205ca2b81 Srikanth Thokala 2015-05-05 2795 static int axienet_probe(struct platform_device *pdev)\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2796 {\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2797 \tint ret;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2798 \tstruct device_node *np;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2799 \tstruct axienet_local *lp;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2800 \tstruct net_device *ndev;\n" + "28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2801 \tstruct resource *ethres;\n" + "83216e3988cd196 Michael Walle 2021-04-12 2802 \tu8 mac_addr[ETH_ALEN];\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 2803 \tint addr_width = 32;\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2804 \tu32 value;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2805 \n" + "808d077f5b53806 Sean Anderson 2026-01-17 2806 \tndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));\n" + "41de8d4cff21a2e Joe Perches 2012-01-29 2807 \tif (!ndev)\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2808 \t\treturn -ENOMEM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2809 \n" + "95219aa538e11d5 Srikanth Thokala 2015-05-05 2810 \tplatform_set_drvdata(pdev, ndev);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2811 \n" + "95219aa538e11d5 Srikanth Thokala 2015-05-05 2812 \tSET_NETDEV_DEV(ndev, &pdev->dev);\n" + "28e24c62ab3062e Eric Dumazet 2013-12-02 2813 \tndev->features = NETIF_F_SG;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2814 \n" + "d894be57ca92c8a Jarod Wilson 2016-10-20 2815 \t/* MTU range: 64 - 9000 */\n" + "d894be57ca92c8a Jarod Wilson 2016-10-20 2816 \tndev->min_mtu = 64;\n" + "d894be57ca92c8a Jarod Wilson 2016-10-20 2817 \tndev->max_mtu = XAE_JUMBO_MTU;\n" + "d894be57ca92c8a Jarod Wilson 2016-10-20 2818 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2819 \tlp = netdev_priv(ndev);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2820 \tlp->ndev = ndev;\n" + "95219aa538e11d5 Srikanth Thokala 2015-05-05 2821 \tlp->dev = &pdev->dev;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2822 \tlp->options = XAE_OPTION_DEFAULTS;\n" + "8b09ca823ffb4ee Robert Hancock 2019-06-06 2823 \tlp->rx_bd_num = RX_BD_NUM_DEFAULT;\n" + "8b09ca823ffb4ee Robert Hancock 2019-06-06 2824 \tlp->tx_bd_num = TX_BD_NUM_DEFAULT;\n" + "57baf8cc70ea4cf Robert Hancock 2021-02-12 2825 \n" + "cb45a8bf4693965 Robert Hancock 2022-08-29 2826 \tu64_stats_init(&lp->rx_stat_sync);\n" + "cb45a8bf4693965 Robert Hancock 2022-08-29 2827 \tu64_stats_init(&lp->tx_stat_sync);\n" + "cb45a8bf4693965 Robert Hancock 2022-08-29 2828 \n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2829 \tmutex_init(&lp->stats_lock);\n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2830 \tseqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock);\n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2831 \tINIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats);\n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2832 \n" + "808d077f5b53806 Sean Anderson 2026-01-17 2833 \tlp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev,\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2834 \t\t\t\t\t\t \"s_axi_lite_clk\");\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2835 \tif (!lp->axi_clk) {\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2836 \t\t/* For backward compatibility, if named AXI clock is not present,\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2837 \t\t * treat the first clock specified as the AXI clock.\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2838 \t\t */\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2839 \t\tlp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);\n" + "57baf8cc70ea4cf Robert Hancock 2021-02-12 2840 \t}\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2841 \tif (IS_ERR(lp->axi_clk))\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2842 \t\treturn dev_err_probe(&pdev->dev, PTR_ERR(lp->axi_clk),\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2843 \t\t\t\t \"could not get AXI clock\\n\");\n" + "57baf8cc70ea4cf Robert Hancock 2021-02-12 2844 \n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2845 \tlp->misc_clks[0].id = \"axis_clk\";\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2846 \tlp->misc_clks[1].id = \"ref_clk\";\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2847 \tlp->misc_clks[2].id = \"mgt_clk\";\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2848 \n" + "808d077f5b53806 Sean Anderson 2026-01-17 2849 \tret = devm_clk_bulk_get_optional_enable(&pdev->dev, XAE_NUM_MISC_CLOCKS,\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2850 \t\t\t\t\t\tlp->misc_clks);\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2851 \tif (ret)\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2852 \t\treturn dev_err_probe(&pdev->dev, ret,\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2853 \t\t\t\t \"could not get/enable misc. clocks\\n\");\n" + "b11bfb9a19f9d79 Robert Hancock 2021-03-25 2854 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2855 \t/* Map device registers */\n" + "47651c51c02fc49 Yang Yingliang 2021-06-10 2856 \tlp->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ðres);\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2857 \tif (IS_ERR(lp->regs))\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2858 \t\treturn PTR_ERR(lp->regs);\n" + "7fa0043d5c74c6e Robert Hancock 2019-06-11 2859 \tlp->regs_start = ethres->start;\n" + "46aa27df8853214 Srikanth Thokala 2015-05-05 2860 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2861 \t/* Setup checksum offload, but default to off if not specified */\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2862 \tlp->features = 0;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2863 \n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2864 \tif (axienet_ior(lp, XAE_ABILITY_OFFSET) & XAE_ABILITY_STATS)\n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2865 \t\tlp->features |= XAE_FEATURE_STATS;\n" + "76abb5d675c49ba Sean Anderson 2024-08-20 2866 \n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2867 \tret = of_property_read_u32(pdev->dev.of_node, \"xlnx,txcsum\", &value);\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2868 \tif (!ret) {\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2869 \t\tswitch (value) {\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2870 \t\tcase 1:\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2871 \t\t\tlp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;\n" + "dd28f4c0e81f42b Sean Anderson 2024-09-09 2872 \t\t\t/* Can checksum any contiguous range */\n" + "dd28f4c0e81f42b Sean Anderson 2024-09-09 2873 \t\t\tndev->features |= NETIF_F_HW_CSUM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2874 \t\t\tbreak;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2875 \t\tcase 2:\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2876 \t\t\tlp->features |= XAE_FEATURE_FULL_TX_CSUM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2877 \t\t\t/* Can checksum TCP/UDP over IPv4. */\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2878 \t\t\tndev->features |= NETIF_F_IP_CSUM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2879 \t\t\tbreak;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2880 \t\t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2881 \t}\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2882 \tret = of_property_read_u32(pdev->dev.of_node, \"xlnx,rxcsum\", &value);\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2883 \tif (!ret) {\n" + "8495659bf93c8e2 Srikanth Thokala 2015-05-05 2884 \t\tswitch (value) {\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2885 \t\tcase 1:\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2886 \t\t\tlp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;\n" + "06c069ff2f7013f Sean Anderson 2024-09-09 2887 \t\t\tndev->features |= NETIF_F_RXCSUM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2888 \t\t\tbreak;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2889 \t\tcase 2:\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2890 \t\t\tlp->features |= XAE_FEATURE_FULL_RX_CSUM;\n" + "06c069ff2f7013f Sean Anderson 2024-09-09 2891 \t\t\tndev->features |= NETIF_F_RXCSUM;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2892 \t\t\tbreak;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2893 \t\t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2894 \t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2895 \t/* For supporting jumbo frames, the Axi Ethernet hardware must have\n" + "f080a8c35d8932d Srikanth Thokala 2015-05-05 2896 \t * a larger Rx/Tx Memory. Typically, the size must be large so that\n" + "f080a8c35d8932d Srikanth Thokala 2015-05-05 2897 \t * we can enable jumbo option and start supporting jumbo frames.\n" + "f080a8c35d8932d Srikanth Thokala 2015-05-05 2898 \t * Here we check for memory allocated for Rx/Tx in the hardware from\n" + "f080a8c35d8932d Srikanth Thokala 2015-05-05 2899 \t * the device-tree and accordingly set flags.\n" + "f080a8c35d8932d Srikanth Thokala 2015-05-05 2900 \t */\n" + "34b270e7893f4a1 Suraj Gupta 2026-08-06 2901 \tret = of_property_read_u32(pdev->dev.of_node, \"xlnx,rxmem\", &lp->rxmem);\n" + "34b270e7893f4a1 Suraj Gupta 2026-08-06 2902 \tif (ret)\n" + "34b270e7893f4a1 Suraj Gupta 2026-08-06 2903 \t\treturn dev_err_probe(&pdev->dev, ret,\n" + "34b270e7893f4a1 Suraj Gupta 2026-08-06 2904 \t\t\t\t \"failed to read xlnx,rxmem property\\n\");\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2905 \n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2906 \tlp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2907 \t\t\t\t\t\t \"xlnx,switch-x-sgmii\");\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2908 \n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2909 \t/* Start with the proprietary, and broken phy_type */\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2910 \tret = of_property_read_u32(pdev->dev.of_node, \"xlnx,phy-type\", &value);\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2911 \tif (!ret) {\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2912 \t\tnetdev_warn(ndev, \"Please upgrade your device tree binary blob to use phy-mode\");\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2913 \t\tswitch (value) {\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2914 \t\tcase XAE_PHY_TYPE_MII:\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2915 \t\t\tlp->phy_mode = PHY_INTERFACE_MODE_MII;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2916 \t\t\tbreak;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2917 \t\tcase XAE_PHY_TYPE_GMII:\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2918 \t\t\tlp->phy_mode = PHY_INTERFACE_MODE_GMII;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2919 \t\t\tbreak;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2920 \t\tcase XAE_PHY_TYPE_RGMII_2_0:\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2921 \t\t\tlp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2922 \t\t\tbreak;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2923 \t\tcase XAE_PHY_TYPE_SGMII:\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2924 \t\t\tlp->phy_mode = PHY_INTERFACE_MODE_SGMII;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2925 \t\t\tbreak;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2926 \t\tcase XAE_PHY_TYPE_1000BASE_X:\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2927 \t\t\tlp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2928 \t\t\tbreak;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2929 \t\tdefault:\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2930 \t\t\treturn -EINVAL;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2931 \t\t}\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2932 \t} else {\n" + "0c65b2b90d13c1d Andrew Lunn 2019-11-04 2933 \t\tret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode);\n" + "0c65b2b90d13c1d Andrew Lunn 2019-11-04 2934 \t\tif (ret)\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2935 \t\t\treturn ret;\n" + "ee06b1728b95643 Alvaro G. M 2017-07-17 2936 \t}\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2937 \tif (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII &&\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2938 \t lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) {\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2939 \t\tdev_err(&pdev->dev, \"xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\\n\");\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2940 \t\treturn -EINVAL;\n" + "6c8f06bb2e5147b Robert Hancock 2021-02-12 2941 \t}\n" "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2942 \n" "5fe164fb0e6e31d Rob Herring (Arm 2024-07-31 2943) \tif (!of_property_present(pdev->dev.of_node, \"dmas\")) {\n" "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2944 \t\t/* Find the DMA node, map the DMA registers, and decode the DMA IRQs */\n" @@ -53,10 +219,7 @@ "28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2964 \t\t\t/* Check for these resources directly on the Ethernet node. */\n" "47651c51c02fc49 Yang Yingliang 2021-06-10 2965 \t\t\tlp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);\n" "28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2966 \t\t\tlp->rx_irq = platform_get_irq(pdev, 1);\n" - " ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n" "28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2967 \t\t\tlp->tx_irq = platform_get_irq(pdev, 0);\n" - " ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n" - "\n" "d6349e3e14c7f7b Andre Przywara 2020-03-24 2968 \t\t\tlp->eth_irq = platform_get_irq_optional(pdev, 2);\n" "28ef9ebdb64c6f4 Robert Hancock 2019-06-06 2969 \t\t}\n" "fcc028c106e5750 Krzysztof Kozlowski 2015-07-09 2970 \t\tif (IS_ERR(lp->dma_regs)) {\n" @@ -64,16 +227,189 @@ "808d077f5b53806 Sean Anderson 2026-01-17 2972 \t\t\treturn PTR_ERR(lp->dma_regs);\n" "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2973 \t\t}\n" "bb2b71024976a39 bui duc phuc 2026-09-09 @2974 \t\tif (!lp->rx_irq || !lp->tx_irq) {\n" - "\n" - "These should be checks for negative instead of zero.\n" - "\n" "95219aa538e11d5 Srikanth Thokala 2015-05-05 2975 \t\t\tdev_err(&pdev->dev, \"could not determine irqs\\n\");\n" "bb2b71024976a39 bui duc phuc 2026-09-09 2976 \t\t\treturn -EINVAL;\n" "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2977 \t\t}\n" "bb2b71024976a39 bui duc phuc 2026-09-09 2978 \t\tif (lp->rx_irq < 0)\n" + "bb2b71024976a39 bui duc phuc 2026-09-09 2979 \t\t\treturn lp->rx_irq;\n" + "bb2b71024976a39 bui duc phuc 2026-09-09 2980 \t\tif (lp->tx_irq < 0)\n" + "bb2b71024976a39 bui duc phuc 2026-09-09 2981 \t\t\treturn lp->tx_irq;\n" + "90ab44517ee1f9e bui duc phuc 2026-09-09 2982 \t\tif (lp->eth_irq < 0 && lp->eth_irq != -ENXIO)\n" + "90ab44517ee1f9e bui duc phuc 2026-09-09 2983 \t\t\treturn lp->eth_irq;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 2984 \n" + "f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2985 \t\t/* Reset core now that clocks are enabled, prior to accessing MDIO */\n" + "f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2986 \t\tret = __axienet_device_reset(lp);\n" + "f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2987 \t\tif (ret)\n" + "808d077f5b53806 Sean Anderson 2026-01-17 2988 \t\t\treturn ret;\n" + "f1bc9fc4a06de01 Maxim Kochetkov 2023-06-22 2989 \n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2990 \t\t/* Autodetect the need for 64-bit DMA pointers.\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2991 \t\t * When the IP is configured for a bus width bigger than 32 bits,\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2992 \t\t * writing the MSB registers is mandatory, even if they are all 0.\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2993 \t\t * We can detect this case by writing all 1's to one such register\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2994 \t\t * and see if that sticks: when the IP is configured for 32 bits\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2995 \t\t * only, those registers are RES0.\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2996 \t\t * Those MSB registers were introduced in IP v7.1, which we check first.\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2997 \t\t */\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2998 \t\tif ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 2999 \t\t\tvoid __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3000 \n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3001 \t\t\tiowrite32(0x0, desc);\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3002 \t\t\tif (ioread32(desc) == 0) {\t/* sanity check */\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3003 \t\t\t\tiowrite32(0xffffffff, desc);\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3004 \t\t\t\tif (ioread32(desc) > 0) {\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3005 \t\t\t\t\tlp->features |= XAE_FEATURE_DMA_64BIT;\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3006 \t\t\t\t\taddr_width = 64;\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3007 \t\t\t\t\tdev_info(&pdev->dev,\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3008 \t\t\t\t\t\t \"autodetected 64-bit DMA range\\n\");\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3009 \t\t\t\t}\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3010 \t\t\t\tiowrite32(0x0, desc);\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3011 \t\t\t}\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3012 \t\t}\n" + "00be43a74ca2622 Andy Chiu 2022-06-13 3013 \t\tif (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) {\n" + "61fde5110ee9f1f Colin Ian King 2025-04-18 3014 \t\t\tdev_err(&pdev->dev, \"64-bit addressable DMA is not compatible with 32-bit architecture\\n\");\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3015 \t\t\treturn -EINVAL;\n" + "00be43a74ca2622 Andy Chiu 2022-06-13 3016 \t\t}\n" + "f735c40ed93ccae Andre Przywara 2020-03-24 3017 \n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3018 \t\tret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width));\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3019 \t\tif (ret) {\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3020 \t\t\tdev_err(&pdev->dev, \"No suitable DMA available\\n\");\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3021 \t\t\treturn ret;\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3022 \t\t}\n" + "6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3023 \t\tnetif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll);\n" + "6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3024 \t\tnetif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll);\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3025 \t} else {\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3026 \t\tstruct xilinx_vdma_config cfg;\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3027 \t\tstruct dma_chan *tx_chan;\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3028 \n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3029 \t\tlp->eth_irq = platform_get_irq_optional(pdev, 0);\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3030 \t\tif (lp->eth_irq < 0 && lp->eth_irq != -ENXIO) {\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3031 \t\t\treturn lp->eth_irq;\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3032 \t\t}\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3033 \t\ttx_chan = dma_request_chan(lp->dev, \"tx_chan0\");\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3034 \t\tif (IS_ERR(tx_chan))\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3035 \t\t\treturn dev_err_probe(lp->dev, PTR_ERR(tx_chan),\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3036 \t\t\t\t\t \"No Ethernet DMA (TX) channel found\\n\");\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3037 \n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3038 \t\tcfg.reset = 1;\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3039 \t\t/* As name says VDMA but it has support for DMA channel reset */\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3040 \t\tret = xilinx_vdma_channel_set_config(tx_chan, &cfg);\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3041 \t\tif (ret < 0) {\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3042 \t\t\tdev_err(&pdev->dev, \"Reset channel failed\\n\");\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3043 \t\t\tdma_release_channel(tx_chan);\n" + "808d077f5b53806 Sean Anderson 2026-01-17 3044 \t\t\treturn ret;\n" + "6b1b40f704fc39d Sarath Babu Naidu Gaddam 2023-11-16 3045 \t\t}\n" + "5fff0151b3244dc Andre Przywara 2020-03-24 3046 \n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3047 \t\tdma_release_channel(tx_chan);\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3048 \t\tlp->use_dmaengine = 1;\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3049 \t}\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3050 \n" + "c1c3d01e3a9038d Suraj Gupta 2026-06-01 3051 \tif (lp->use_dmaengine) {\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3052 \t\tndev->netdev_ops = &axienet_netdev_dmaengine_ops;\n" + "c1c3d01e3a9038d Suraj Gupta 2026-06-01 3053 \t\tndev->ethtool_ops = &axienet_ethtool_dmaengine_ops;\n" + "c1c3d01e3a9038d Suraj Gupta 2026-06-01 3054 \t} else {\n" + "6a91b846af85a24 Radhey Shyam Pandey 2023-11-16 3055 \t\tndev->netdev_ops = &axienet_netdev_ops;\n" + "c1c3d01e3a9038d Suraj Gupta 2026-06-01 3056 \t\tndev->ethtool_ops = &axienet_ethtool_ops;\n" + "c1c3d01e3a9038d Suraj Gupta 2026-06-01 3057 \t}\n" + "522856cefaf09d1 Robert Hancock 2019-06-06 3058 \t/* Check for Ethernet core IRQ (optional) */\n" + "2d2f18d49221846 bui duc phuc 2026-09-09 3059 \tif (lp->eth_irq < 0)\n" + "522856cefaf09d1 Robert Hancock 2019-06-06 3060 \t\tdev_info(&pdev->dev, \"Ethernet core IRQ not defined\\n\");\n" + "522856cefaf09d1 Robert Hancock 2019-06-06 3061 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3062 \t/* Retrieve the MAC address */\n" + "83216e3988cd196 Michael Walle 2021-04-12 3063 \tret = of_get_mac_address(pdev->dev.of_node, mac_addr);\n" + "83216e3988cd196 Michael Walle 2021-04-12 3064 \tif (!ret) {\n" + "da90e38003e2f05 Tobias Klauser 2016-12-07 3065 \t\taxienet_set_mac_address(ndev, mac_addr);\n" + "83216e3988cd196 Michael Walle 2021-04-12 3066 \t} else {\n" + "83216e3988cd196 Michael Walle 2021-04-12 3067 \t\tdev_warn(&pdev->dev, \"could not find MAC address property: %d\\n\",\n" + "83216e3988cd196 Michael Walle 2021-04-12 3068 \t\t\t ret);\n" + "83216e3988cd196 Michael Walle 2021-04-12 3069 \t\taxienet_set_mac_address(ndev, NULL);\n" + "83216e3988cd196 Michael Walle 2021-04-12 3070 \t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3071 \n" + "d048c717df33baf Sean Anderson 2025-02-06 3072 \tspin_lock_init(&lp->rx_cr_lock);\n" + "d048c717df33baf Sean Anderson 2025-02-06 3073 \tspin_lock_init(&lp->tx_cr_lock);\n" + "e1d27d29dbe5139 Sean Anderson 2025-02-06 3074 \tINIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work);\n" + "e1d27d29dbe5139 Sean Anderson 2025-02-06 3075 \tlp->rx_dim_enabled = true;\n" + "e1d27d29dbe5139 Sean Anderson 2025-02-06 3076 \tlp->rx_dim.profile_ix = 1;\n" + "e1d27d29dbe5139 Sean Anderson 2025-02-06 3077 \tlp->rx_dma_cr = axienet_calc_cr(lp, axienet_dim_coalesce_count_rx(lp),\n" + "eb80520e8a5be67 Sean Anderson 2025-02-06 3078 \t\t\t\t\tXAXIDMA_DFT_RX_USEC);\n" + "eb80520e8a5be67 Sean Anderson 2025-02-06 3079 \tlp->tx_dma_cr = axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD,\n" + "eb80520e8a5be67 Sean Anderson 2025-02-06 3080 \t\t\t\t\tXAXIDMA_DFT_TX_USEC);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3081 \n" + "09a0354cadec267 Robert Hancock 2019-06-06 3082 \tret = axienet_mdio_setup(lp);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3083 \tif (ret)\n" + "09a0354cadec267 Robert Hancock 2019-06-06 3084 \t\tdev_warn(&pdev->dev,\n" + "09a0354cadec267 Robert Hancock 2019-06-06 3085 \t\t\t \"error registering MDIO bus: %d\\n\", ret);\n" + "d1c4f93e3f0a023 Andy Chiu 2022-04-05 3086 \n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3087 \tif (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3088 \t lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3089 \t\tnp = of_parse_phandle(pdev->dev.of_node, \"pcs-handle\", 0);\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3090 \t\tif (!np) {\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3091 \t\t\t/* Deprecated: Always use \"pcs-handle\" for pcs_phy.\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3092 \t\t\t * Falling back to \"phy-handle\" here is only for\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3093 \t\t\t * backward compatibility with old device trees.\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3094 \t\t\t */\n" + "ab3a5d4c6081dbc Andy Chiu 2022-04-05 3095 \t\t\tnp = of_parse_phandle(pdev->dev.of_node, \"phy-handle\", 0);\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3096 \t\t}\n" + "ab3a5d4c6081dbc Andy Chiu 2022-04-05 3097 \t\tif (!np) {\n" + "19c7a43912c61a3 Andy Chiu 2022-04-05 3098 \t\t\tdev_err(&pdev->dev, \"pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\\n\");\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3099 \t\t\tret = -EINVAL;\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3100 \t\t\tgoto cleanup_mdio;\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3101 \t\t}\n" + "ab3a5d4c6081dbc Andy Chiu 2022-04-05 3102 \t\tlp->pcs_phy = of_mdio_find_device(np);\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3103 \t\tif (!lp->pcs_phy) {\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3104 \t\t\tret = -EPROBE_DEFER;\n" + "ab3a5d4c6081dbc Andy Chiu 2022-04-05 3105 \t\t\tof_node_put(np);\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3106 \t\t\tgoto cleanup_mdio;\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3107 \t\t}\n" + "ab3a5d4c6081dbc Andy Chiu 2022-04-05 3108 \t\tof_node_put(np);\n" + "7a86be6a5135eaa Russell King (Oracle 2022-01-25 3109) \t\tlp->pcs.ops = &axienet_pcs_ops;\n" + "7a86be6a5135eaa Russell King (Oracle 2022-01-25 3110) \t\tlp->pcs.poll = true;\n" + "1a02556086fc0eb Robert Hancock 2020-10-28 3111 \t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3112 \n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3113 \tlp->phylink_config.dev = &ndev->dev;\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3114 \tlp->phylink_config.type = PHYLINK_NETDEV;\n" + "a370295367b5566 Nick Hu 2025-02-17 3115 \tlp->phylink_config.mac_managed_pm = true;\n" + "72a47e1aaf2e05e Russell King (Oracle 2021-11-16 3116) \tlp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |\n" + "72a47e1aaf2e05e Russell King (Oracle 2021-11-16 3117) \t\tMAC_10FD | MAC_100FD | MAC_1000FD;\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3118 \n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3119) \t__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3120) \tif (lp->switch_x_sgmii) {\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3121) \t\t__set_bit(PHY_INTERFACE_MODE_1000BASEX,\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3122) \t\t\t lp->phylink_config.supported_interfaces);\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3123) \t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3124) \t\t\t lp->phylink_config.supported_interfaces);\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3125) \t}\n" + "136a3fa28a9f562 Russell King (Oracle 2021-11-16 3126) \n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3127 \tlp->phylink = phylink_create(&lp->phylink_config, pdev->dev.fwnode,\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3128 \t\t\t\t lp->phy_mode,\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3129 \t\t\t\t &axienet_phylink_ops);\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3130 \tif (IS_ERR(lp->phylink)) {\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3131 \t\tret = PTR_ERR(lp->phylink);\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3132 \t\tdev_err(&pdev->dev, \"phylink_create error (%i)\\n\", ret);\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3133 \t\tgoto cleanup_mdio;\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3134 \t}\n" + "f5203a3d9b25fa2 Robert Hancock 2019-06-06 3135 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3136 \tret = register_netdev(lp->ndev);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3137 \tif (ret) {\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3138 \t\tdev_err(lp->dev, \"register_netdev() error (%i)\\n\", ret);\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3139 \t\tgoto cleanup_phylink;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3140 \t}\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3141 \n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3142 \treturn 0;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3143 \n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3144 cleanup_phylink:\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3145 \tphylink_destroy(lp->phylink);\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3146 \n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3147 cleanup_mdio:\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3148 \tif (lp->pcs_phy)\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3149 \t\tput_device(&lp->pcs_phy->dev);\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3150 \tif (lp->mii_bus)\n" + "59cd4f19267a0aa Robert Hancock 2021-03-11 3151 \t\taxienet_mdio_teardown(lp);\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3152 \treturn ret;\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3153 }\n" + "8a3b7a252dca9fb Daniel Borkmann 2012-01-19 3154 \n" "\n" "--\n" "0-DAY CI Kernel Test Service\n" https://github.com/intel/lkp-tests/wiki -a1b3fedf4c3891a845cdf7f04c93b77c59c3d194fa13fd7fe3312dcfa79fd30f +134d053ad5c262791171155f57f011cd998ff34abc530f356421929fcfd8e435
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