From: sashiko-bot@kernel.org
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH 5/5] PCI/quirks: Avoid certain BAR 0 address with igb
Date: Wed, 23 Sep 2026 13:29:04 +0000 [thread overview]
Message-ID: <20260923132904.CF0231F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260923131757.7792-6-ilpo.jarvinen@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] pci: skipping hardware update in bar0_address_breakage() causes desync
- [High] pci: ignoring pci_release_resource() return corrupts tree
--
commit 140645b0838c61616e4734fb4c852db528a2c054
Author: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Date: Wed Sep 23 13:17:55 2026 +0000
PCI/quirks: Avoid certain BAR 0 address with igb
This patch adds a quirk to reshuffle igb resources when BAR 0 is placed at
0x9c000000, which previously caused the driver to fail during probe due to
unexpected reads. The quirk uses BAR 3 to block the problematic address by
relocating it.
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index de9bbccda21fd..e6f3e2ab1fd4e 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
[ ... ]
> @@ -6288,6 +6288,62 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
[ ... ]
> +static void bar0_address_breakage(struct pci_dev *dev)
> +{
[ ... ]
> + pci_dev_for_each_resource(dev, res, i) {
> + if (!resource_assigned(res) ||
> + resource_type(res) != IORESOURCE_MEM)
> + continue;
> +
> + pci_release_resource(dev, i);
[Severity: High]
Can ignoring the return value of pci_release_resource() cause tree
corruption?
If a resource fails to release (e.g., returning -EBUSY), it remains actively
linked in the system's resource sibling tree. The code below then modifies
its boundaries unconditionally via resource_set_range().
Does modifying the start and end bounds of a node while it is still linked
violate the strict address-ordered sibling list invariants of the resource
tree, and cause pci_claim_resource() to corrupt pointers by re-inserting it?
> + }
> +
> + resource_set_range(bar3, broken_addr, resource_size(bar3));
> + bar3->flags &= ~IORESOURCE_UNSET;
> + pci_claim_resource(dev, 3);
> + if (!resource_assigned(bar3)) {
> + bar3->flags |= IORESOURCE_UNSET;
> + pci_warn(dev, "resource relocation failed\n");
> + }
> +
> + pci_dev_for_each_resource(dev, res, i) {
> + if (resource_assigned(res) ||
> + resource_type(res) != IORESOURCE_MEM)
> + continue;
> +
> + ret = pci_assign_resource(dev, i);
[Severity: High]
Does skipping BAR 3 in this loop cause a desync between the software
resource tree and the physical hardware?
Since pci_claim_resource() updates the software resource tree but does not
write to the physical hardware PCI configuration registers, the hardware BAR
needs to be updated.
However, because BAR 3 was claimed and marked assigned in software earlier,
the resource_assigned() check skips it here. This permanently bypasses the
hardware register update.
Would this leave the OS thinking BAR 3 is at 0x9c000000 while the physical
hardware remains at its old address, causing the MSI-X table reads to fail
and creating a possible PCIe bus conflict?
> + if (ret)
> + pci_warn(dev, "resource relocation failed\n");
> + }
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260923131757.7792-1-ilpo.jarvinen@linux.intel.com?part=5
next prev parent reply other threads:[~2026-09-23 13:29 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260923131757.7792-1-ilpo.jarvinen@linux.intel.com>
2026-09-23 13:17 ` [PATCH 2/5] PCI: Fix nesting windows with remainder at the left edge Ilpo Järvinen
2026-09-23 13:32 ` sashiko-bot
2026-09-23 13:17 ` [PATCH 3/5] PCI: Place resources to either edge of the window Ilpo Järvinen
2026-09-23 13:28 ` sashiko-bot
2026-09-24 11:03 ` Ilpo Järvinen
2026-09-23 13:17 ` [PATCH 4/5] PCI: Fix composite resource sizing Ilpo Järvinen
2026-09-23 13:31 ` sashiko-bot
2026-09-23 13:39 ` Ilpo Järvinen
2026-09-23 13:17 ` [PATCH 5/5] PCI/quirks: Avoid certain BAR 0 address with igb Ilpo Järvinen
2026-09-23 13:29 ` sashiko-bot [this message]
2026-09-24 20:20 ` Bjorn Helgaas
2026-09-28 12:20 ` Ilpo Järvinen
2026-09-28 13:19 ` David Laight
2026-09-28 14:30 ` Ilpo Järvinen
2026-09-28 18:56 ` David Laight
2026-09-26 2:00 ` [PATCH 0/5] PCI: Resource placement algorithm fixes Nikolas Joshua Britton
2026-09-28 12:34 ` Ilpo Järvinen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260923132904.CF0231F00898@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=linux-pci@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.