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From: sashiko-bot@kernel.org
To: "Karthik Poosa" <karthik.poosa@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
Date: Thu, 24 Sep 2026 11:27:34 +0000	[thread overview]
Message-ID: <20260924112734.ACC9F1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260924111156.2628915-12-karthik.poosa@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] hwmon: xe: incorrect IEEE-754 decoding applied to VRAM_N on Crescent Island
--

commit 8039331718fb03f6dfcbe8bbe7a3375383a0c5d2
Author: Karthik Poosa <karthik.poosa@intel.com>

drm/xe/hwmon: Decode CRI temperature registers as IEEE-754

This commit decodes the package and VRAM temperatures on Crescent Island
from an IEEE-754 floating-point format to integer millidegrees.

> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index e1cff5700e7f9..c411cd375aa1b 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c

[ ... ]

> @@ -1249,26 +1312,27 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  	switch (attr) {
>  	case hwmon_temp_input:
>  		switch (channel) {
> -		case CHANNEL_PKG:
> -		case CHANNEL_VRAM:
> -			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -
> -			/* HW register value is in degrees Celsius, convert to millidegrees. */
> -			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> -			return 0;
>  		case CHANNEL_MCTRL:
>  			return get_mc_temp(hwmon, val);
>  		case CHANNEL_PCIE:
>  			return get_pcie_temp(hwmon, val);
> +		case CHANNEL_PKG:
> +		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -			/*
> -			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> -			 * [7:0] fraction.
> -			 */
> -			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
> -				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> -				 MILLIDEGREE_PER_DEGREE;
> +			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +				return xe_hwmon_temperature_decode((u32)reg_val, val);

[Severity: Medium]
Will this indiscriminately apply IEEE-754 decoding to all VRAM channels on
Crescent Island, including CHANNEL_VRAM_N?

Looking at xe_hwmon_get_reg(), VRAM_N on XE_CRESCENTISLAND still uses
the legacy BMG_VRAM_TEMPERATURE_N registers:

	case REG_TEMP:
		if (xe->info.platform == XE_CRESCENTISLAND) {
			if (channel == CHANNEL_PKG)
				...
			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);

Since BMG_VRAM_TEMPERATURE_N registers encode temperatures in a 24.8
fixed-point format, parsing them as IEEE-754 floating-point values will
result in incorrectly reporting sensor values when reading tempN_input via
sysfs.

Could this condition be narrowed to exclude CHANNEL_VRAM_N?

> +			} else if (channel >= CHANNEL_VRAM_N) {
> +				/*
> +				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> +				 * [7:0] fraction for platforms before CRI.
> +				 */
> +				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
> +					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> +					MILLIDEGREE_PER_DEGREE;
> +			} else {
> +				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> +			}
>  			return 0;
>  		default:
>  			return -EOPNOTSUPP;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260924111156.2628915-1-karthik.poosa@intel.com?part=11

  reply	other threads:[~2026-09-24 11:27 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-24 11:11 [PATCH v5 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-09-24 11:23   ` sashiko-bot
2026-09-24 14:26     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-09-24 11:24   ` sashiko-bot
2026-09-24 11:11 ` [PATCH v5 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-09-24 11:24   ` sashiko-bot
2026-09-24 13:16     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 09/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-09-24 11:24   ` sashiko-bot
2026-09-24 13:40     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 10/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-09-24 11:27   ` sashiko-bot
2026-09-24 13:41     ` Poosa, Karthik
2026-09-24 11:11 ` [PATCH v5 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-24 11:27   ` sashiko-bot [this message]
2026-09-24 11:11 ` [PATCH v5 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-09-24 11:11 ` [PATCH v5 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
2026-09-24 11:40 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev2) Patchwork
2026-09-24 12:56 ` ✓ Xe.CI.BAT: " Patchwork

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