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charset="UTF-8" Save and restore the AER mask, severity, capability and root command registers through the per-device saved capability store instead of a private pci_cap_saved_state buffer. Describe the registers in aer_saved_regs[] and drive the reservation, save, and restore loops from it. Previously the three had to be kept in the same order by hand, and pci_aer_init() encoded the register count as a bare 4 or 5. Report a reservation failure. pci_aer_init() ignored the return value of pci_add_ext_cap_save_buffer() entirely, so a failed allocation was only noticed later as silently missing AER state. No functional change intended. Assisted-by: LLM Signed-off-by: David Matlack --- drivers/pci/pcie/aer.c | 79 +++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d8dcd238fda1..765899cf4046 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -352,53 +352,53 @@ int pci_aer_clear_status(struct pci_dev *dev) return pci_aer_raw_clear_status(dev); } -void pci_save_aer_state(struct pci_dev *dev) +/* + * AER registers saved and restored by the PCI core. PCI_ERR_ROOT_COMMAND is + * only implemented by Root Ports and Root Complex Event Collectors (PCIe + * r6.0, sec 7.8.4.9) and so must come last. + */ +static const u16 aer_saved_regs[] = { + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNCOR_SEVER, + PCI_ERR_COR_MASK, + PCI_ERR_CAP, + PCI_ERR_ROOT_COMMAND, +}; + +static unsigned int aer_nr_saved_regs(struct pci_dev *dev) { - int aer = dev->aer_cap; - struct pci_cap_saved_state *save_state; - u32 *cap; + if (pcie_cap_has_rtctl(dev)) + return ARRAY_SIZE(aer_saved_regs); - if (!aer) - return; + return ARRAY_SIZE(aer_saved_regs) - 1; +} + +void pci_save_aer_state(struct pci_dev *dev) +{ + unsigned int i; - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); - if (!save_state) + if (!dev->aer_cap) return; - cap = &save_state->cap.data[0]; - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); - pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); - if (pcie_cap_has_rtctl(dev)) - pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); + for (i = 0; i < aer_nr_saved_regs(dev); i++) + pci_save_cap_dword(dev, dev->aer_cap + aer_saved_regs[i]); } void pci_restore_aer_state(struct pci_dev *dev) { - int aer = dev->aer_cap; - struct pci_cap_saved_state *save_state; - u32 *cap; + unsigned int i; - if (!aer) - return; - - save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); - if (!save_state) + if (!dev->aer_cap) return; - cap = &save_state->cap.data[0]; - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); - pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); - if (pcie_cap_has_rtctl(dev)) - pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); + for (i = 0; i < aer_nr_saved_regs(dev); i++) + pci_restore_cap_dword(dev, dev->aer_cap + aer_saved_regs[i]); } void pci_aer_init(struct pci_dev *dev) { - int n; + unsigned int i; + int error; dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (!dev->aer_cap) @@ -415,14 +415,15 @@ void pci_aer_init(struct pci_dev *dev) ratelimit_state_init(&dev->aer_info->nonfatal_ratelimit, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); - /* - * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, - * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event - * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r6.0, sec - * 7.8.4.9). - */ - n = pcie_cap_has_rtctl(dev) ? 5 : 4; - pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); + for (i = 0; i < aer_nr_saved_regs(dev); i++) { + unsigned int off = dev->aer_cap + aer_saved_regs[i]; + + error = pci_reserve_saved_cap(dev, off, sizeof(u32)); + if (error) { + pci_err(dev, "unable to reserve AER save state\n"); + break; + } + } /* * Advisory Non-Fatal Errors are masked by default (PCIe r7.0, sec -- 2.56.0.rc1.315.gc6ed9934b7-goog