From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrey Ryabinin <ryabinin.a.a@gmail.com>,
Alexander Potapenko <glider@google.com>,
Andrey Konovalov <andreyknvl@gmail.com>,
Dmitry Vyukov <dvyukov@google.com>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kasan-dev@googlegroups.com
Subject: Re: [PATCH v3 4/5] riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57
Date: Fri, 25 Sep 2026 15:43:24 +0100 [thread overview]
Message-ID: <20260925-stuffing-lunar-5a44380ebaf1@spud> (raw)
In-Reply-To: <20260909150158.9313-5-jszhang@kernel.org>
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Acked-by: Conor Dooley <conor.dooley@microchip.com>
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next prev parent reply other threads:[~2026-09-25 14:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 15:01 [PATCH v3 0/5] optimize pgtable_l4|l5_enabled Jisheng Zhang
2026-09-09 15:01 ` [PATCH v3 1/5] riscv: remove RISCV_ALTERNATIVE Kconfig option Jisheng Zhang
2026-09-09 15:01 ` [PATCH v3 2/5] riscv: convert pgtable_l4|l5_enabled to inline function Jisheng Zhang
2026-09-09 15:01 ` [PATCH v3 3/5] riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled Jisheng Zhang
2026-09-25 15:01 ` Conor Dooley
2026-09-09 15:01 ` [PATCH v3 4/5] riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57 Jisheng Zhang
2026-09-25 14:43 ` Conor Dooley [this message]
2026-09-09 15:01 ` [PATCH v3 5/5] riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled Jisheng Zhang
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