From: sashiko-bot@kernel.org
To: "Andre Przywara" <andre.przywara@arm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v3 2/5] net: phy: Add support for the Maxio MAE0621A
Date: Sun, 27 Sep 2026 23:01:48 +0000 [thread overview]
Message-ID: <20260927230148.E497E1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260926225625.25969-3-andre.przywara@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] net: phy: maxio: potential configuration loss from soft reset
--
commit fe4e6c1e8992faa353fc23228a8b3ebe634a12dd
Author: Liu Changjie <liucj1228@outlook.com>
net: phy: Add support for the Maxio MAE0621A
This commit adds a new driver for the Maxio MAE0621A Gigabit Ethernet PHY.
It introduces exact PHY ID matching and an optional configuration to enable
a 125 MHz clock on the CLKOUT pin based on device properties.
> diff --git a/drivers/net/phy/maxio.c b/drivers/net/phy/maxio.c
> new file mode 100644
> index 0000000000000..d2cb238956460
> --- /dev/null
> +++ b/drivers/net/phy/maxio.c
[ ... ]
> +static int maxio_mae0621a_config_init(struct phy_device *phydev)
> +{
> + struct maxio_priv *priv = phydev->priv;
> + int ret;
> +
> + if (!priv->clk_out_125m)
> + return 0;
> +
> + ret = phy_modify_paged_changed(phydev, MAXIO_MAE0621A_PHYCR2_PAGE,
> + MAXIO_MAE0621A_PHYCR2,
> + MAXIO_MAE0621A_CLKOUT_ENABLE |
> + MAXIO_MAE0621A_CLKOUT_125M,
> + MAXIO_MAE0621A_CLKOUT_ENABLE |
> + MAXIO_MAE0621A_CLKOUT_125M);
> + if (ret <= 0)
> + return ret;
> +
> + return genphy_soft_reset(phydev);
[Severity: Medium]
Does this soft reset potentially clear the vendor-specific paged register
configuration that was just applied?
IEEE 802.3 Clause 22 states that BMCR_RESET resets control registers to
their default values. While some PHYs retain their paged vendor configurations
across a soft reset, others wipe all registers. If the MAE0621A PHY clears
vendor pages during a soft reset, the newly applied
MAXIO_MAE0621A_CLKOUT_125M configuration in maxio_mae0621a_config_init()
might be silently reverted to its default state.
Could you confirm if this specific hardware retains the PHYCR2 register state
after genphy_soft_reset()?
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260926225625.25969-1-andre.przywara@arm.com?part=2
next prev parent reply other threads:[~2026-09-27 23:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-26 22:56 [PATCH net-next v3 0/5] net: phy: Add Maxio MAE0621A support Andre Przywara
2026-09-26 22:56 ` [PATCH net-next v3 1/5] dt-bindings: net: Add Maxio MAE0621A PHY Andre Przywara
2026-09-26 22:56 ` [PATCH net-next v3 2/5] net: phy: Add support for the Maxio MAE0621A Andre Przywara
2026-09-27 17:23 ` Andrew Lunn
2026-09-27 23:01 ` sashiko-bot [this message]
2026-09-26 22:56 ` [PATCH net-next v3 3/5] net: phy: maxio: prepare for more DT properties Andre Przywara
2026-09-27 17:31 ` Andrew Lunn
2026-09-26 22:56 ` [PATCH net-next v3 4/5] net: phy: maxio: parse and enable PHY clock from generic DT binding Andre Przywara
2026-09-27 17:29 ` Andrew Lunn
2026-09-27 23:01 ` sashiko-bot
2026-09-26 22:56 ` [PATCH net-next v3 5/5] net: phy: maxio: add support for -Q2C variant Andre Przywara
2026-09-27 17:31 ` Andrew Lunn
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