Re: [PATCH 11/15] perf/x86/intel: Fix invalid PEBS counts with counter-group support

[sashiko-bot@kernel.org]

> On platforms with PEBS counter-group support (for example ARL and NVL),
> running mixed PEBS events can occasionally produce an invalidly large
> count for the instructions event, even exceeding the hardware counter
> width (48 bits).
> 
> $ perf record -e '{cpu_core/instructions,period=100000/u,\
> 	cpu_core/l1-icache-load-misses,period=100000/u}:pS' -- ./foo
> 
> The issue is caused by PEBS drain ordering. To avoid scanning the PEBS
> buffer twice, current drain helpers defer each event's last PEBS record
> and do not process all records strictly in sampling order. That is safe
> when no counter-group PEBS event is involved, but it can corrupt PEBS
> count updates when two or more active PEBS events use counter-group
> snapshotting.
> 
> Add intel_pmu_handle_pebs_records_in_order() and use it when two or more
> counter-group PEBS events are active, so records are processed strictly in
> sampling order for both adaptive PEBS and arch PEBS. This preserves
> correct count updates and prevents invalid PEBS counts.
> 
> Fixes: 8807d922705f ("perf/x86/intel/ds: Factor out PEBS record processing code to functions")
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260928074309.898043-1-dapeng1.mi@linux.intel.com?part=11