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LX2160A: > a) Eight 64-bit ARM v8 Cortex-A72 CPUs > > +SerDes 1 lane grouping > + SRDS_PRTCL_S1 is latched at reset. U-Boot can still configure SD1 before > + the MC starts: > + 1x100GE + 4x25G, 2x40GE, 1x40GE + 4x10G or 1x100GE + 4x10G. > + See 'serdes1' in doc/README.fsl-hwconfig, and the 'lx2160_serdes status' > + command. > + > > LS1028A > -------- > diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig > index e752505da49..3f9d2ddad75 100644 > --- a/doc/README.fsl-hwconfig > +++ b/doc/README.fsl-hwconfig > @@ -44,3 +44,63 @@ usb > usb1:dr_mode=host;usb2:dr_mode=peripheral' > > usb1:dr_mode=host,phy_type=utmi;usb2:dr_mode=host' > + > +serdes1 > + Specific to the LX2160A boards whose reset_phy() calls > + lx2160a_serdes_apply_hwconfig() before mc_env_boot(): lx2160aqds. > + > + SRDS_PRTCL_S1 is latched at reset, but the eight SD1 (SerDes) lanes > + can still be configured before the DPAA2 management complex (MC) starts. > + This option picks the grouping. The RCW, and RCWSR29, keep the > + protocol number. I feel the last 2 sentences do not have a sharply defined meaning. Maybe say "This option alters the Ethernet MAC-to-lane grouping after the fact (RCWSR29 will continue reporting the initial protocol)"? > + > + 'serdes1:2x100g' > + 2x 100GE (CAUI-4), what protocol 13 builds: nothing to do > + > + 'serdes1:100g4x25g' > + 1x 100GE + 4x 25G > + > + 'serdes1:2x40g' > + 2x 40GE (XLAUI-4) > + > + 'serdes1:40g4x10g' > + 1x 40GE + 4x 10G (XFI) > + > + 'serdes1:100g4x10g' > + 1x 100GE + 4x 10G (XFI) > + > + Each mode starts from the one in the 'from' column, which is > + entered first when SD1 is not in it yet, and so on down to what > + SRDS_PRTCL_S1 built: > + > + mode from SRDS_PRTCL_S1 lanes run on > + 2x100g - 13 PLLF > + 100g4x25g 2x100g 13 PLLF > + 2x40g 2x100g 13 PLLS > + 40g4x10g 2x40g 13 or 20 PLLS > + 100g4x10g 2x100g 13 PLLF and PLLS > + > + What each mode makes of the two four-lane ports of protocol 13: > + > + mode dpmac.2 port dpmac.1 port > + 2x100g 100GE 100GE > + 100g4x25g 100GE 4x 25G: dpmac.3 to dpmac.6 > + 2x40g 40GE 40GE > + 40g4x10g 40GE 4x XFI: dpmac.3 to dpmac.6 > + 100g4x10g 100GE 4x XFI: dpmac.3 to dpmac.6 > + > + Initial conditions: > + > + - The MC must not be running yet. Otherwise the mode is refused and > + SD1 is left as it is. What is actionable for the reader with this information? Assuming the reader is a board user, and not a developer. BTW, the first paragraph already says "Specific to the LX2160A boards whose reset_phy() calls lx2160a_serdes_apply_hwconfig() before mc_env_boot()". > + - The MC DPC must set follow_hw_pssr in board_info/serdes, for the > + MC to read the lanes rather than look at protocol, and the DPL > + must use the dpmacs of the new grouping. - PLLS must be provisioned with a refclk frequency from which the 10.3125 GHz clock net can be derived. This is kind of important, because this requirement does not exist on the native SRDS_PRTCL_S1=13 boot, because there, PLLS is simply powered down. You just _assume_ you can power it up and it will lock at the frequency you want. > + > + 'lx2160_serdes status 1' shows the resulting lane grouping and > + protocol converters. > + > + Example: > + setenv hwconfig serdes1:100g4x25g > + saveenv > + reset > -- > 2.43.0 >