Re: [PATCH 2/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Yazen Ghannam <yazen.ghannam@amd.com>]

On Mon, Sep 28, 2026 at 12:20:45PM -0700, Borislav Petkov wrote:
> On Mon, Sep 28, 2026 at 10:38:21AM -0400, Yazen Ghannam wrote:
> > I didn't consider this a necessary fix. But it'd be good to have it to
> > avoid noise from reports.
> 
> I didn't either but what is Vishal doing to trigger this:
> 
> "Since only four csrows are allocated, a syndrome with bit 2 set decodes
> to an out-of-range csrow and trips:
> 
>   EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)"
> 
> Vishal?
> 
> From reading the commit message, I still have no clue how that happens and
> what are we fixing here.
> 

There are a couple of cases that trip this.

1) Newer hardware where 'bit 2' is redefined. For example, it could mean
'sub-channel' or something else relevant. In that case, a real error
would be decoded incorrectly.

2) Some hardware error injection methods that use arbitrary values. This
is like the 'error simulation' we do in the mce-inject module where we
can write something to the registers.

So the patch is a fix for #2 today, and it is a preemptive fix for #1.

Thanks,
Yazen