From: sashiko-bot@kernel.org
To: "Santhosh Kumar K" <s-k6@ti.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v10 03/19] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz
Date: Tue, 29 Sep 2026 06:48:54 +0000 [thread overview]
Message-ID: <20260929064855.0FB271F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260929063529.1235417-4-s-k6@ti.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] spi: missing bounds check for post_config_max_speed_hz
- [Medium] spi: missing propagation of post_config_max_speed_hz to non-DT instantiations
- [Medium] spi: proxy and ancillary devices drop post_config_max_speed_hz
--
commit a54a647ebbac4cf4a270dd8915b629161a216725
Author: Santhosh Kumar K <s-k6@ti.com>
Subject: spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz
This patch adds post_config_max_speed_hz to struct spi_device and parses
it from the spi-max-post-config-frequency-hz device tree property. This
supports SPI devices that operate at a conservative rate before
configuration and a higher rate after controller-side configuration.
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index 015d93680e5d0..97bf58dacd06d 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -2809,6 +2809,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
> /* Device speed */
> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> spi->max_speed_hz = value;
> + if (!of_property_read_u32(nc, "spi-max-post-config-frequency-hz", &value))
> + spi->post_config_max_speed_hz = value;
[Severity: Medium]
Does limiting this new property to device tree via of_property_read_u32()
prevent ACPI and software nodes from using it? The core pattern usually
relies on device_property_read_u32() in __spi_add_device() to support
these automatically.
Also, should spi_board_info be updated to propagate this configuration to
non-DT SPI instantiations? Currently, spi_new_device() maps fields from
spi_board_info to spi_device like this:
drivers/spi/spi.c:spi_new_device() {
...
proxy->max_speed_hz = chip->max_speed_hz;
proxy->mode = chip->mode;
proxy->irq = chip->irq;
...
}
Does this omission mean devices instantiated via spi_register_board_info()
or ACPI cannot configure post-configuration high-speed capabilities?
[Severity: High]
Is a bounds check needed for post_config_max_speed_hz against the
controller's maximum speed? In __spi_setup(), spi->max_speed_hz is correctly
capped:
drivers/spi/spi.c:__spi_setup() {
...
if (spi->controller->max_speed_hz &&
(!spi->max_speed_hz ||
spi->max_speed_hz > spi->controller->max_speed_hz))
spi->max_speed_hz = spi->controller->max_speed_hz;
...
}
Without a similar check for post_config_max_speed_hz, could a device tree
misconfiguration instruct the SPI controller to drive a clock frequency
exceeding its physical hardware limits, potentially leading to invalid
divider calculations or hardware lockups?
[Severity: Medium]
Should post_config_max_speed_hz also be propagated to proxy and ancillary
devices? When an ancillary device is created, max_speed_hz and mode are
copied, but post_config_max_speed_hz is omitted:
drivers/spi/spi.c:spi_new_ancillary_device() {
...
ancillary->max_speed_hz = spi->max_speed_hz;
ancillary->mode = spi->mode;
...
}
Similarly, in drivers/spi/spi-mux.c, the child device's settings are copied
to the multiplexed proxy device:
drivers/spi/spi-mux.c:spi_mux_select() {
...
priv->spi->max_speed_hz = spi->max_speed_hz;
priv->spi->mode = spi->mode;
priv->spi->bits_per_word = spi->bits_per_word;
...
}
Will this omission silently break the ability of multiplexed or ancillary
devices to use PHY tuning and high-speed post-config rates?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260929063529.1235417-1-s-k6@ti.com?part=3
next prev parent reply other threads:[~2026-09-29 6:48 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 6:35 [PATCH v10 00/19] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 01/19] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 02/19] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 03/19] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:48 ` sashiko-bot [this message]
2026-09-29 6:35 ` [PATCH v10 04/19] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:51 ` sashiko-bot
2026-09-29 6:35 ` [PATCH v10 05/19] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 06/19] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 07/19] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:51 ` sashiko-bot
2026-09-29 6:35 ` [PATCH v10 08/19] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:57 ` sashiko-bot
2026-09-29 6:35 ` [PATCH v10 09/19] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 10/19] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 11/19] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:59 ` sashiko-bot
2026-09-29 6:35 ` [PATCH v10 12/19] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 7:00 ` sashiko-bot
2026-09-29 6:35 ` [PATCH v10 13/19] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 14/19] spi: cadence-quadspi: reprogram PHY DLL on runtime resume Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 15/19] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 16/19] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 17/19] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 18/19] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
2026-09-29 6:35 ` [PATCH v10 19/19] mtd: spi-nor: reset max_read_op frequency for security register reads Santhosh Kumar K
2026-09-29 6:35 ` Santhosh Kumar K
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