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Tue, 29 Sep 2026 01:38:20 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Frank Li , Arnd Bergmann , Niklas Cassel , Christian Bruel , Senchuan Zhang , Vincent Guittot , Randolph Lin , Xincheng Zhang , Alex Elder , Siddharth Vadapalli , Andy Shevchenko , Marek Vasut , Inochi Amaoto , Vidya Sagar , Pengpeng Hou , Anirudh Srinivasan , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v7 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Date: Tue, 29 Sep 2026 16:37:51 +0800 Message-ID: <20260929083755.458238-6-inochiama@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260929083755.458238-1-inochiama@gmail.com> References: <20260929083755.458238-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, with some extra link and reset state control. Signed-off-by: Inochi Amaoto --- .../bindings/pci/spacemit,k1-pcie-host.yaml | 55 ++++++++++++++++--- 1 file changed, 46 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml index c4c00b5fcdc0..af32e427c0c5 100644 --- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 PCI Express Host Controller +title: SpacemiT K1/K3 PCI Express Host Controller maintainers: - Alex Elder @@ -12,28 +12,32 @@ maintainers: description: > The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP. The controller uses the DesignWare built-in MSI interrupt - controller, and supports 256 MSIs. - -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# + controller, and supports 256 MSIs. The K3 controller uses an + external MSI interrupt controller and may use multiple PHYs. properties: compatible: - const: spacemit,k1-pcie + enum: + - spacemit,k1-pcie + - spacemit,k3-pcie reg: + minItems: 4 items: - description: DesignWare PCIe registers - description: ATU address space - description: PCIe configuration space - description: Link control registers + - description: Data Bus Interface (DBI) shadow registers. reg-names: + minItems: 4 items: - const: dbi - const: atu - const: config - const: link + - const: dbi2 clocks: items: @@ -66,6 +70,8 @@ properties: interrupt-names: const: msi + msi-parent: true + spacemit,apmu: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -84,7 +90,8 @@ patternProperties: properties: phys: - maxItems: 1 + minItems: 1 + maxItems: 6 vpcie3v3-supply: description: @@ -96,13 +103,43 @@ patternProperties: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: spacemit,k1-pcie + then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 + + patternProperties: + '^pcie@': + properties: + phys: + maxItems: 1 + + required: + - interrupts + - interrupt-names + else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + required: - clocks - clock-names - resets - reset-names - - interrupts - - interrupt-names - spacemit,apmu unevaluatedProperties: false -- 2.55.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1F83CA5FA5 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, with some extra link and reset state control. Signed-off-by: Inochi Amaoto --- .../bindings/pci/spacemit,k1-pcie-host.yaml | 55 ++++++++++++++++--- 1 file changed, 46 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml index c4c00b5fcdc0..af32e427c0c5 100644 --- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 PCI Express Host Controller +title: SpacemiT K1/K3 PCI Express Host Controller maintainers: - Alex Elder @@ -12,28 +12,32 @@ maintainers: description: > The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP. The controller uses the DesignWare built-in MSI interrupt - controller, and supports 256 MSIs. - -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# + controller, and supports 256 MSIs. The K3 controller uses an + external MSI interrupt controller and may use multiple PHYs. properties: compatible: - const: spacemit,k1-pcie + enum: + - spacemit,k1-pcie + - spacemit,k3-pcie reg: + minItems: 4 items: - description: DesignWare PCIe registers - description: ATU address space - description: PCIe configuration space - description: Link control registers + - description: Data Bus Interface (DBI) shadow registers. reg-names: + minItems: 4 items: - const: dbi - const: atu - const: config - const: link + - const: dbi2 clocks: items: @@ -66,6 +70,8 @@ properties: interrupt-names: const: msi + msi-parent: true + spacemit,apmu: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -84,7 +90,8 @@ patternProperties: properties: phys: - maxItems: 1 + minItems: 1 + maxItems: 6 vpcie3v3-supply: description: @@ -96,13 +103,43 @@ patternProperties: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: spacemit,k1-pcie + then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 + + patternProperties: + '^pcie@': + properties: + phys: + maxItems: 1 + + required: + - interrupts + - interrupt-names + else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + required: - clocks - clock-names - resets - reset-names - - interrupts - - interrupt-names - spacemit,apmu unevaluatedProperties: false -- 2.55.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv