From: sashiko-bot@kernel.org
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: imx@lists.linux.dev, vkoul@kernel.org,
devicetree@vger.kernel.org, dmaengine@vger.kernel.org,
Frank.Li@kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v2 2/3] dmaengine: fsl-edma: support per-channel DT child nodes
Date: Wed, 30 Sep 2026 06:42:23 +0000 [thread overview]
Message-ID: <20260930064224.59C941F00899@smtp.kernel.org> (raw)
In-Reply-To: <20260930-edma-iommu-v2-2-72a62bf44c74@nxp.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] dmaengine: fsl-edma: kernel panic due to post-registration dev->bus modification
- [High] dmaengine: fsl-edma: probe deferral masked in DT IRQ lookup
- [Low] dmaengine: fsl-edma: compilation failure due to undefined function and member
--
commit 7b47892ce3017d20fbf0bc531e1531f30816d5d2
Author: Peng Fan <peng.fan@nxp.com>
dmaengine: fsl-edma: support per-channel DT child nodes
This commit adds support for parsing per-channel child nodes from the
devicetree. It configures per-channel IRQs and IOMMUs based on the child
properties. Existing devicetrees without child nodes continue to work as
before.
> diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
> index d9fb717b5b53c..e7e5b33cfcb20 100644
> --- a/drivers/dma/fsl-edma-main.c
> +++ b/drivers/dma/fsl-edma-main.c
[ ... ]
> @@ -695,6 +699,133 @@ static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_eng
[ ... ]
> +static int fsl_edma_configure_chan_from_dt(struct platform_device *pdev,
> + struct fsl_edma_engine *fsl_edma)
> +{
[ ... ]
> + for_each_available_child_of_node(np, child) {
> + struct fsl_edma_chan *fsl_chan;
> + int ch_id, irq;
[ ... ]
> + fsl_chan = &fsl_edma->chans[ch_id];
> +
> + irq = of_irq_get(child, 0);
> + if (irq > 0) {
> + fsl_chan->txirq = irq;
> + fsl_chan->irq_handler = fsl_edma3_tx_handler;
> + }
[Severity: High]
If of_irq_get() returns -EPROBE_DEFER because the interrupt controller
is not yet ready, it seems that error code is silently dropped since
only irq > 0 is checked.
Later in fsl_edma3_irq_init(), if fsl_chan->txirq <= 0, it tries to fall
back to platform_get_irq() which will fail because the interrupts are
defined in the child nodes.
Would this cause fsl_edma3_irq_init() to return -EINVAL, permanently failing
the probe instead of correctly deferring it?
> + }
> +
> + return 0;
> +}
> +
> +static int fsl_edma_configure_chan_iommu(struct platform_device *pdev,
> + struct fsl_edma_engine *fsl_edma)
> +{
[ ... ]
> + for_each_available_child_of_node(np, child) {
> + struct fsl_edma_chan *fsl_chan;
> + int ch_id;
[ ... ]
> + list_for_each_entry(chan, &fsl_edma->dma_dev.channels,
> + device_node) {
> + struct device *chdev;
> +
> + if (to_fsl_edma_chan(chan) != fsl_chan)
> + continue;
> +
> + chdev = dmaengine_chan_dev(chan);
[Severity: Low]
Does dmaengine_chan_dev() exist in the kernel?
It looks like this might cause a compilation failure because the function is
undefined.
> + chdev->bus = pdev->dev.bus;
[Severity: High]
Is it safe to modify the bus of an already-registered device here?
Since fsl_edma_configure_chan_iommu() is called after
dmaenginem_async_device_register(), bus_add_device() has already seen a
NULL bus during registration and skipped incrementing the subsystem reference
count.
If probe fails or the driver unbinds later, device_del() will call
bus_remove_device(), which will see this newly assigned bus and attempt to
drop the reference twice.
Could this cause a use-after-free panic in the bus subsystem?
> + if (fsl_edma->drvdata->flags & FSL_EDMA_DRV_TCD64)
> + dma_coerce_mask_and_coherent(chdev,
> + DMA_BIT_MASK(64));
> + else
> + dma_coerce_mask_and_coherent(chdev,
> + DMA_BIT_MASK(32));
> + ret = of_dma_configure(chdev, child, true);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "IOMMU config failed for channel %d: %d\n",
> + ch_id, ret);
> + of_node_put(child);
> + return ret;
> + }
> +
> + chan->chan_dev->chan_dma_dev = true;
[Severity: Low]
Does struct dma_chan have a member named chan_dev?
This looks like it will cause another compilation failure.
> + break;
> + }
> + }
> +
> + return 0;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260930-edma-iommu-v2-0-72a62bf44c74@nxp.com?part=2
next prev parent reply other threads:[~2026-09-30 6:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 6:26 [PATCH v2 0/3] dmaengine: fsl-edma: per-channel IOMMU support via DT child nodes Peng Fan (OSS)
2026-09-30 6:26 ` [PATCH v2 1/3] dt-bindings: dma: fsl,edma: add per-channel child node support Peng Fan (OSS)
2026-09-30 6:34 ` sashiko-bot
2026-09-30 16:00 ` Frank Li
2026-09-30 6:26 ` [PATCH v2 2/3] dmaengine: fsl-edma: support per-channel DT child nodes Peng Fan (OSS)
2026-09-30 6:42 ` sashiko-bot [this message]
2026-09-30 6:26 ` [PATCH v2 3/3] arm64: dts: imx95: convert eDMA to per-channel " Peng Fan (OSS)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260930064224.59C941F00899@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Frank.Li@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmaengine@vger.kernel.org \
--cc=imx@lists.linux.dev \
--cc=peng.fan@oss.nxp.com \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.