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From: sashiko-bot@kernel.org
To: "Kyle Switch" <kyle.switch@motor-comm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH net-next v22 2/3] net: phy: Add support for Template Control register for PMA
Date: Wed, 30 Sep 2026 10:00:16 +0000	[thread overview]
Message-ID: <20260930100016.B09971F00898@smtp.kernel.org> (raw)
In-Reply-To: <20260929095430.508657-3-kyle.switch@motor-comm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] uapi: kernel-internal GENMASK used in uapi header breaks userspace compilation
- [Low] net: phy: 'template' is a misnomer for standard 10GBASE-T test mode
--

commit b002860110e66ac77172a47fcc853ce9025d5816
Author: Kyle Switch <kyle.switch@motor-comm.com>

net: phy: Add support for Template Control register for PMA
    
Add support for the 10GBASE-T PMA Template Test Mode register
field, which allows selecting one of eight test modes (Normal and
TestMode1..TestMode7) used for PHY validation.

> diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
> index 870920311f9a0..c5f5753f7194b 100644
> --- a/drivers/net/phy/phy-c45.c
> +++ b/drivers/net/phy/phy-c45.c

[ ... ]

> @@ -1408,6 +1408,29 @@ int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
>  }
>  EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
>  
> +/**
> + * genphy_c45_template_testmode - configure template testmode registers
> + * @phydev: target phy_device struct
> + * @test_mode: testmode includes Normal to Test mode 7
> + *
> + * Description: Set template testmode include Normal to Test mode 7
> + *
> + * Return: 0 on success, or a negative error code on failure (e.g. register
> + * read/write error).
> + */
> +int genphy_c45_template_testmode(struct phy_device *phydev, u16 test_mode)

[Severity: Low]
Does the word "template" accurately reflect the IEEE 802.3 standard?

The IEEE 802.3 standard (Clause 45.2.1.75) defines this as the 10GBASE-T
test mode register. Using the word "template" in the core PHY API and UAPI
comments appears to be a misnomer that could cause confusion, as it is not
part of the standard nomenclature.

> +{
> +	u16 ctrl;
> +
> +	if (test_mode > MDIO_PMA_10GBT_TESTMODE_7)
> +		return -EOPNOTSUPP;
> +
> +	ctrl = FIELD_PREP(MDIO_PMA_10GBT_TESTMODE_MASK, test_mode);
> +	return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TESTMODE,
> +			      MDIO_PMA_10GBT_TESTMODE_MASK, ctrl);
> +}
> +EXPORT_SYMBOL_GPL(genphy_c45_template_testmode);

[ ... ]

> diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
> index 06f4bc3c20c71..353ca13c64fca 100644
> --- a/include/uapi/linux/mdio.h
> +++ b/include/uapi/linux/mdio.h

[ ... ]

> @@ -320,6 +321,17 @@
>  /* PMA 10GBASE-R Fast Retrain status and control register. */
>  #define MDIO_PMA_10GBR_FSRT_ENABLE	0x0001	/* Fast retrain enable */
>  
> +/* PMA 10GBASE-T Template Test Mode Register*/
> +#define MDIO_PMA_10GBT_TESTMODE_MASK GENMASK(15, 13) /* Template test mode */

[Severity: High]
Will exposing the kernel-internal GENMASK macro in a UAPI header cause
compilation failures for userspace programs?

Userspace applications including linux/mdio.h will fail to compile because
GENMASK is defined in linux/bits.h, which is not available to userspace.
UAPI headers must use __GENMASK instead.

> +#define MDIO_PMA_10GBT_TESTMODE_NORMAL 0x0 /* Template Normal */
> +#define MDIO_PMA_10GBT_TESTMODE_1 0x1 /* Template TestMode1 */
> +#define MDIO_PMA_10GBT_TESTMODE_2 0x2 /* Template TestMode2 */
> +#define MDIO_PMA_10GBT_TESTMODE_3 0x3 /* Template TestMode3 */
> +#define MDIO_PMA_10GBT_TESTMODE_4 0x4 /* Template TestMode4 */
> +#define MDIO_PMA_10GBT_TESTMODE_5 0x5 /* Template TestMode5 */
> +#define MDIO_PMA_10GBT_TESTMODE_6 0x6 /* Template TestMode6 */
> +#define MDIO_PMA_10GBT_TESTMODE_7 0x7 /* Template TestMode7 */

[Severity: High]
Since kernel helpers like FIELD_PREP are not available in userspace, does
providing these unshifted constants without a corresponding shift macro force
userspace applications to hardcode the shifts when using them?

>  /* PCS 10GBASE-R/-T status register 1. */
>  #define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */
>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260929095430.508657-1-kyle.switch@motor-comm.com?part=2

  parent reply	other threads:[~2026-09-30 10:00 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-29  9:54 [PATCH net-next v22 0/3] net: phy: Add driver for Motorcomm Quad 2.5GbE phy Kyle Switch
2026-09-29  9:54 ` [PATCH net-next v22 1/3] dt-bindings: net: Document Motorcomm YT8824 PHY package Kyle Switch
2026-10-01  9:54   ` netdev-bot+sashiko
2026-09-29  9:54 ` [PATCH net-next v22 2/3] net: phy: Add support for Template Control register for PMA Kyle Switch
2026-09-29 12:00   ` Andrew Lunn
2026-09-30 10:00   ` sashiko-bot [this message]
2026-10-01  9:54   ` netdev-bot+sashiko
2026-09-29  9:54 ` [PATCH net-next v22 3/3] net: phy: Add driver for Motorcomm Quad 2.5GbE phy Kyle Switch
2026-09-29 12:18   ` Andrew Lunn
2026-09-30  0:39     ` Kyle Switch
2026-10-01  9:54   ` netdev-bot+sashiko

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