Re: [PATCH 05/13] drm/msm/dp: Unwind resources when enabling a stream fails

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/msm/dp: missing clear of DPCD training pattern on retrain failure
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commit 9215bc6b24d793ba7f4c076d150d2b4195e8af3e
Author: Xilin Wu <sophon@radxa.com>

drm/msm/dp: Unwind resources when enabling a stream fails

This patch adds tracking for DP stream power references and link startup 
to properly unwind resources on failure. It consolidates the rollback 
path and propagates error codes from PHY initialization, power-on, and 
stream retraining.

> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
[ ... ]
> @@ -2583,8 +2595,11 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl,
>  		}
>  	}
>  
> -	if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl))
> -		msm_dp_ctrl_link_retrain(ctrl, panel);
> +	if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) {
> +		ret = msm_dp_ctrl_link_retrain(ctrl, panel);
> +		if (ret)
> +			return ret;
> +	}
>  
>  	/* stop txing train pattern to end link training */
>  	msm_dp_ctrl_clear_training_pattern(ctrl, panel, DP_PHY_DPRX);

[Severity: Medium]
Does this early return skip clearing the training pattern on the DP sink?

When msm_dp_ctrl_link_retrain() fails and returns an error, the function 
now returns early and bypasses the required call to 
msm_dp_ctrl_clear_training_pattern(). 

This leaves the DP sink in an incomplete link training state because the 
DPCD DP_TRAINING_PATTERN_SET register is not explicitly reset to 
DP_TRAINING_PATTERN_DISABLE. 

Could this cause the sink to malfunction, remain blank, or become 
unresponsive on subsequent link initialization attempts? Should the hardware 
training state be cleared before propagating the error?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260930-msm-dp-hdr10-v1-0-dbbf8b2b42bc@radxa.com?part=5