Re: [PATCH 6/6] arm64: dts: qcom: hawi: Add QPaCE DT node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: qpace interrupt index mismatch
--

commit d697c8786fb69e9e9786a688577373ec76f73ba9
Author: Georgi Djakov <georgi.djakov@oss.qualcomm.com>

arm64: dts: qcom: hawi: Add QPaCE DT node

Add the device-tree node for the Qualcomm Page Compression Engine on
the Hawi platform.

> diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
> index 6b0a0ff0faa45..283a5acfa0738 100644
> --- a/arch/arm64/boot/dts/qcom/hawi.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
> @@ -5677,6 +5677,23 @@ llclpi_noc: interconnect@31310000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		qpace: compression@31400000 {
> +			compatible = "qcom,hawi-qpace";
> +			reg = <0x0 0x31400000 0x0 0x80000>;
> +			iommus = <&apps_smmu 0x1c20 0x13>,
> +				 <&apps_smmu 0x1c24 0x13>,
> +				 <&apps_smmu 0x1c28 0x13>,
> +				 <&apps_smmu 0x1c2c 0x13>;
> +			dma-coherent;
> +			interconnects = <&gem_noc MASTER_QPACE QCOM_ICC_TAG_ALWAYS
> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "qpace-mem";
> +			interrupts = <GIC_ESPI 72 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_ESPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "ring-and-bus-err",
> +					  "urgent";

[Severity: Medium]
Will this interrupt mapping cause an IRQ storm?

Looking at drivers/soc/qcom/qpace.c in qpace_register_interrupts(), the
driver fetches the urgent interrupt by index 0 (QPACE_IRQ_URGENT = 0):

enum qpace_interrupts {
	QPACE_IRQ_URGENT
};

static int qpace_register_interrupts(struct platform_device *pdev)
{
	...
	irq = platform_get_irq(pdev, QPACE_IRQ_URGENT);

However, this device tree node places the urgent interrupt at index 1.

This would cause the driver to bind its urgent interrupt handler to the
ring-and-bus-err interrupt instead.

When an urgent completion IRQ fires (ESPI 71), it will be unhandled,
eventually causing an IRQ storm that the kernel must forcibly disable.
Meanwhile, error interrupts (ESPI 72) will incorrectly trigger the urgent
handler.

> +		};
> +
>  		system-cache-controller@31800000 {
>  			compatible = "qcom,hawi-llcc";
>  			reg = <0x0 0x31800000 0x0 0x200000>,

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260930145215.3380977-1-georgi.djakov@oss.qualcomm.com?part=6