From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06BD22EEE63; Wed, 30 Sep 2026 17:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790790331; cv=none; b=GrZ3G3EPbsxtcfdxvhvlMpqKXHbWZmvKQ5yISLPcU9asjE5WDei7IEh1ZYh+znQBM7auSj9o9N7ryvO5gzpAk92pWAC6TOFUsa6l6/gzq46VRtsrtb2q2zVhLXB/mWARl06c2C+QRX687T/Klcv3FUbaCIj/Wyn7PTn3b5jR3vY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790790331; c=relaxed/simple; bh=49c+G1J73zDhfkPdIU3NBI1Zfn9k21gTNSOwDHAxVD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MbU6paLY7QjvvnSxZkXtSj80cBclwgoLdJvC6q93s+4cxsfeSKXgpHxe4UmufZXmbtHWeL+oHfPCRoTKjmWlIad8rmgs9Mu6pmlkMzdMb5dvRuZ52rCdNUNC1o1n6+Wk5vXrHJ9kaL7mFVBT+KEZZ31KN3+zbij/hhm9V6bLO0k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=bgn6JO/P; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="bgn6JO/P" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B2E51F000FF; Wed, 30 Sep 2026 17:45:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1790790329; bh=xzUx+RyWNb0+x1HiTtUvWFtkqN04lqQMP2ILJxthxAg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bgn6JO/PEMON4HHlO5QJm8TgtcBGc5E9inmiqevlta/7hLg/M+uD4HqmyA0An1fWX hQ/1+MwR/TSvf3tvRix5QfBguw0uzKwJZmWwTIn39Ga/UKt52jxrPNjTHBkfjU3b5Q P1OXmb5XyY9BOG9ixXSkMUkVI0+kMGb/G1Iqy1KI= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , Jinjie Ruan , Ada Couprie Diaz , Ard Biesheuvel , Catalin Marinas , James Morse , Marc Zyngier , Peter Zijlstra , Vladimir Murzin , Will Deacon , Yang Shi , Sasha Levin Subject: [PATCH 6.12 792/877] arm64: percpu: Fix LSE operations on {8,16}-bit types Date: Wed, 30 Sep 2026 17:28:23 +0200 Message-ID: <20260930152431.805309898@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260930152414.738996857@linuxfoundation.org> References: <20260930152414.738996857@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Mark Rutland [ Upstream commit 8cf2093f5372952a9ebc805c418d45df7112cd14 ] The assembly for __percpu_##name##_case_##sz() and __percpu_##name##_return_case_##sz() doesn't use the 'sfx' macro argument to form the LSE instruction. Without 'sfx', a W register argument will imply a 32-bit memory location, and consequently {8,16}-bit ops will erroneously read and write 32 bits of memory when the LSE instruction is used. Fix this by appending 'sfx' to 'op_lse' to LSE instruction. It is not necessary (and not valid) to append 'sfx' to 'op_llsc', as 'op_llsc' is a register-register operation which does not access memory (and does not take a size suffix). Fixes: 959bf2fd03b5 ("arm64: percpu: Rewrite per-cpu ops to allow use of LSE atomics") Signed-off-by: Mark Rutland Reviewed-by: Jinjie Ruan Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: James Morse Cc: Marc Zyngier Cc: Peter Zijlstra Cc: Vladimir Murzin Cc: Will Deacon Cc: Yang Shi Cc: stable@vger.kernel.org Reviewed-by: Vladimir Murzin Signed-off-by: Will Deacon Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/percpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -77,7 +77,7 @@ __percpu_##name##_case_##sz(void *ptr, u " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \ " cbnz %w[loop], 1b", \ /* LSE atomics */ \ - #op_lse "\t%" #w "[val], %" #w "[tmp], %[ptr]\n" \ + #op_lse #sfx "\t%" #w "[val], %" #w "[tmp], %[ptr]\n" \ __nops(3)) \ : [loop] "=&r" (loop), [tmp] "=&r" (tmp), \ [ptr] "+Q"(*(u##sz *)ptr) \ @@ -98,7 +98,7 @@ __percpu_##name##_return_case_##sz(void " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \ " cbnz %w[loop], 1b", \ /* LSE atomics */ \ - #op_lse "\t%" #w "[val], %" #w "[ret], %[ptr]\n" \ + #op_lse #sfx "\t%" #w "[val], %" #w "[ret], %[ptr]\n" \ #op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \ __nops(2)) \ : [loop] "=&r" (loop), [ret] "=&r" (ret), \