Re: [PATCH] serial: tegra: don't clear the Tx FIFO on an Rx-only reset

[sashiko-bot@kernel.org]

> tegra_uart_fifo_reset() applies the Tegra30 workaround for
> "cannot clear the Tx FIFO while FIFO mode is enabled"
> unconditionally: it leaves FIFO mode, writes the requested FCR
> clear bits, and re-enters FIFO mode. Leaving FIFO mode empties
> both FIFOs, so an Rx-only reset discards queued Tx data as well.
> 
> The break handler in tegra_uart_decode_rx_error() calls it with
> UART_FCR_CLEAR_RCVR only. On a half-duplex RS485 board whose Rx
> line is pulled low while the transceiver drives the bus, every
> transmission raises a spurious break, and all but the first
> character of the frame is lost.
> 
> Only take the FIFO-mode path when the caller actually asked for
> CLEAR_XMIT. Likewise only wait for TEMT in that case: with the Tx
> FIFO deliberately left intact, that loop would otherwise spin for
> a full frame time in hard IRQ context with the port lock held.
> 
> Tested on a Colibri T30 (Tegra30) with Rx DMA:
> 
>  - Break during transmission: the reset still fires from
>    tegra_uart_decode_rx_error(), and the complete frame now
>    reaches the peer. Before this change only the character in
>    the shift register was sent.
>  - Internal loopback with a generated break: the Rx FIFO is
>    correctly cleared by the plain FCR write, and subsequent
>    receive works with no frame, parity or overrun errors.
> 
> Fixes: e9ea096dd225 ("serial: tegra: add serial driver")
> Cc: stable@vger.kernel.org
> Signed-off-by: Simon Gassner <simon.gassner@noxsystems.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20261001060539.32659-1-simon.gassner@noxsystems.com?part=1