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From: David Rosca <david.rosca@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: David Rosca <david.rosca@amd.com>
Subject: [PATCH] drm/amdgpu: Allow VCE SEI command in IB
Date: Fri, 2 Oct 2026 16:52:49 +0200	[thread overview]
Message-ID: <20261002145248.30879-2-david.rosca@amd.com> (raw)

Mesa will use it to get the slice offset in bitstream from feedback,
which makes it possible to filter out SPS/PPS headers that VCE 1 and 2
FW always forces on IDR frames.

Signed-off-by: David Rosca <david.rosca@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 39d87f3df9e0..bfad44ec7feb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -920,6 +920,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p,
 		case 0x04000007: /* motion estimation */
 		case 0x04000008: /* rdo */
 		case 0x04000009: /* vui */
+		case 0x0400000d: /* sei */
 		case 0x05000002: /* auxiliary buffer */
 		case 0x05000009: /* clock table */
 			break;
-- 
2.43.0


             reply	other threads:[~2026-10-02 14:53 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-02 14:52 David Rosca [this message]
2026-10-02 15:34 ` [PATCH] drm/amdgpu: Allow VCE SEI command in IB Alex Deucher
2026-10-05 16:10   ` David Rosca

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