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Fri, 02 Oct 2026 09:47:49 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xCgQG-000000008FP-19Pb; Fri, 02 Oct 2026 13:47:48 -0300 Date: Fri, 2 Oct 2026 13:47:48 -0300 From: Jason Gunthorpe To: Nicolin Chen Cc: Pranjal Shrivastava , iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Radu Rendec , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , rafael@kernel.org, Danilo Krummrich , driver-core@lists.linux.dev Subject: Re: [PATCH v11 11/16] iommu/arm-smmu-v3: Add CMDQ_PROD_STOP_FLAG to gate CMDQ submissions Message-ID: <20261002164748.GD3481470@ziepe.ca> References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-12-praan@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Oct 01, 2026 at 11:03:15AM -0700, Nicolin Chen wrote: > > So we can't issue ATC_INVs during suspend (the EP is already down), nor > > during resume (the SMMU resumes *before* the EP is made active). The EP > > can't use its ATC while suspended, and if it loses power/resets on the > > way back to D0 (from D3cold, or D3hot with No_Soft_Reset=0), it comes > > back with an empty ATC.. same assumption the PCI reset path makes today > > (pci_dev_reset_iommu_prepare()). > > In that case, would the STOP flag be too late? It's only set in > the middle of the SMMU suspend. So, an ATC command (via doamin > invalidation) might be issued prior to the Point of Commitment, > which will be timed out due to the unresponding EP? How can you ever fix that? How does power management really work, is it expected that the end device is already quieted by its driver? Could the first step in power management install a blocked STE? Then we don't have to worry about ATC desync and that automatically stops generating new ATC invalidations if we go and detact the domains too Maybe I'm wondering if power management should involve the core code so it detaches all the domains from the device, setups up blocking and then the iommu itself could power ofF? Jason