[drm-amdgpu:drm-amdgpu-next 43/174] drivers/gpu/drm/amd/amdgpu/ih_v8_0.c:412:16: sparse: sparse: cast to restricted __le32

[kernel test robot <lkp@intel.com>]

tree:   https://gitlab.freedesktop.org/drm/amdgpu/kernel drm-amdgpu-next
head:   b596733c95f394cc304f590dabe3bc218f88158e
commit: 327edf9e92d8dc992532b39f4542b537a6a5122f [43/174] drm/amdgpu: Add ih v8_0 support
config: microblaze-randconfig-r2309-20261002 (https://download.01.org/0day-ci/archive/20261002/202610021704.tBU4uCyL-lkp@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 8.5.0
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261002/202610021704.tBU4uCyL-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610021704.tBU4uCyL-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/amdgpu/ih_v8_0.c:412:16: sparse: sparse: cast to restricted __le32
>> drivers/gpu/drm/amd/amdgpu/ih_v8_0.c:509:25: sparse: sparse: incorrect type in initializer (different base types) @@     expected unsigned int [usertype] wptr @@     got restricted __le32 [usertype] @@
   drivers/gpu/drm/amd/amdgpu/ih_v8_0.c:509:25: sparse:     expected unsigned int [usertype] wptr
   drivers/gpu/drm/amd/amdgpu/ih_v8_0.c:509:25: sparse:     got restricted __le32 [usertype]

vim +412 drivers/gpu/drm/amd/amdgpu/ih_v8_0.c

   394	
   395	/**
   396	 * ih_v8_0_get_wptr() - get the IH ring buffer wptr
   397	 *
   398	 * @adev: amdgpu_device pointer
   399	 * @ih: IH ring buffer to fetch wptr
   400	 *
   401	 * Get the IH ring buffer wptr from either the register
   402	 * or the writeback memory buffer.  Also check for
   403	 * ring buffer overflow and deal with it.
   404	 * Returns the value of the wptr.
   405	 */
   406	static u32 ih_v8_0_get_wptr(struct amdgpu_device *adev,
   407				      struct amdgpu_ih_ring *ih)
   408	{
   409		u32 wptr, tmp;
   410		struct amdgpu_ih_regs *ih_regs;
   411	
 > 412		wptr = le32_to_cpu(*ih->wptr_cpu);
   413		ih_regs = &ih->ih_regs;
   414	
   415		if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
   416			goto out;
   417	
   418		wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
   419		if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
   420			goto out;
   421		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
   422	
   423		/* When a ring buffer overflow happen start parsing interrupt
   424		 * from the last not overwritten vector (wptr + 32). Hopefully
   425		 * this should allow us to catch up.
   426		 */
   427		tmp = (wptr + 32) & ih->ptr_mask;
   428		dev_warn(adev->dev, "IH ring buffer overflow "
   429			 "(0x%08X, 0x%08X, 0x%08X)\n",
   430			 wptr, ih->rptr, tmp);
   431		ih->rptr = tmp;
   432	
   433		tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
   434		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
   435		WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
   436	
   437		/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
   438		 * can be detected.
   439		 */
   440		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
   441		WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
   442	out:
   443		return (wptr & ih->ptr_mask);
   444	}
   445	
   446	/**
   447	 * ih_v8_0_irq_rearm - rearm IRQ if lost
   448	 *
   449	 * @adev: amdgpu_device pointer
   450	 * @ih: IH ring to match
   451	 *
   452	 */
   453	static void ih_v8_0_irq_rearm(struct amdgpu_device *adev,
   454				      struct amdgpu_ih_ring *ih)
   455	{
   456		uint32_t v = 0;
   457		uint32_t i = 0;
   458		struct amdgpu_ih_regs *ih_regs;
   459	
   460		ih_regs = &ih->ih_regs;
   461	
   462		/* Rearm IRQ / re-write doorbell if doorbell write is lost */
   463		for (i = 0; i < MAX_REARM_RETRY; i++) {
   464			v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
   465			if ((v < ih->ring_size) && (v != ih->rptr))
   466				WDOORBELL32(ih->doorbell_index, ih->rptr);
   467			else
   468				break;
   469		}
   470	}
   471	
   472	/**
   473	 * ih_v8_0_set_rptr - set the IH ring buffer rptr
   474	 *
   475	 * @adev: amdgpu_device pointer
   476	 * @ih: IH ring buffer to set rptr
   477	 */
   478	static void ih_v8_0_set_rptr(struct amdgpu_device *adev,
   479				     struct amdgpu_ih_ring *ih)
   480	{
   481		struct amdgpu_ih_regs *ih_regs;
   482	
   483		if (ih->use_doorbell) {
   484			/* XXX check if swapping is necessary on BE */
   485			*ih->rptr_cpu = ih->rptr;
   486			WDOORBELL32(ih->doorbell_index, ih->rptr);
   487	
   488			if (amdgpu_sriov_vf(adev))
   489				ih_v8_0_irq_rearm(adev, ih);
   490		} else {
   491			ih_regs = &ih->ih_regs;
   492			WREG32(ih_regs->ih_rb_rptr, ih->rptr);
   493		}
   494	}
   495	
   496	/**
   497	 * ih_v8_0_self_irq - dispatch work for ring 1
   498	 *
   499	 * @adev: amdgpu_device pointer
   500	 * @source: irq source
   501	 * @entry: IV with WPTR update
   502	 *
   503	 * Update the WPTR from the IV and schedule work to handle the entries.
   504	 */
   505	static int ih_v8_0_self_irq(struct amdgpu_device *adev,
   506				    struct amdgpu_irq_src *source,
   507				    struct amdgpu_iv_entry *entry)
   508	{
 > 509		uint32_t wptr = cpu_to_le32(entry->src_data[0]);
   510	
   511		switch (entry->ring_id) {
   512		case 1:
   513			*adev->irq.ih1.wptr_cpu = wptr;
   514			schedule_work(&adev->irq.ih1_work);
   515			break;
   516		default: break;
   517		}
   518		return 0;
   519	}
   520	

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