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Fri, 2 Oct 2026 14:33:01 -0500 Received: from roman-vdev.amd.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Fri, 2 Oct 2026 14:32:55 -0500 From: To: CC: Harry Wentland , Leo Li , Roman Li , Wayne Lin , Tom Chung , Fangzhi Zuo , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Roman Li Subject: [PATCH 00/17] DC Patches October 2, 2026 Date: Fri, 2 Oct 2026 15:32:23 -0400 Message-ID: <20261002193240.3441018-1-Roman.Li@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BD8:EE_|CH0PR12MB8506:EE_ X-MS-Office365-Filtering-Correlation-Id: 8847c581-79a2-4f8a-2c81-08df20bbf990 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|376014|23010399003|1800799024|10067099003|56012099006|11063799006|3023799007|18002099003|6133799003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aGIxQGCUGf+OD0wQWCgxkHqGqnfFlrBmePcD/JhU6xej4Qr1Mxv8GB5LDnJBmG+Ys7yfaSma9dXmK5IEhYvGY3gNGSa1XvLapDdpyIiiyOMvlUl6LfUJGCVii403nxBSOqt7RTdvRPc3wPOcRvvd31giFixPszV456+xfVmNQsgIxOtZIHmtuXrDjgs+bCzutKltHLR9/VVe+Fh7FnxARTwh2iOBJGOq64w2u6CTuLb393xO8Mbj1IItUzktLzXv/vN7DUJomUryl8SmoGHDoe0xAWLWVUWIXINGl/9OCrit47mvMYrAMGYgiJ84KnWpnG7k4zDFXmNps95in1ibkIpEDTzDmKJigGJ7wRB/2O2aT9InHX1hgUlWm2mpTmA9gpq/i+r7a5ez3h8nxMI+7P8AMMP/1npfviYreLd246hCPWaeurUjEQyobnVva2bl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2026 19:33:02.7403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8847c581-79a2-4f8a-2c81-08df20bbf990 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BD8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8506 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Roman Li This DC 3.2.401 patchset brings improvements in multiple areas. In summary, we have: * HDMI: RR and SCDC skips, link-training timeout behaviour, VRR metadata in the VTEM info packet, and a TMDS output regression revert; * MCM shaper/3DLUT programming and DTN logging improvements; * DMUB: fast-lock sequencing refactor and FAMS2 command update; * DSC configuration preparation and DRR reprogramming optimizations; * Replay/low-power, eDP link-bandwidth, cursor offload, and virtual link encoder handling; * New DCN42b project ID. Cc: Dan Wheeler Allen Li (1): drm/amd/display: Skip link off frame count for general UI Alvin Lee (3): drm/amd/display: Set cursor_offload for all pipes for a given stream drm/amd/display: Assign alt wa bit in fams2 cmd drm/amd/display: Add debug option to override low power SR latencies Aric Cyr (1): drm/amd/display: only reprogram DRR when v_total values change Ashwin Santhosh (1): drm/amd/display: Promote DC to 3.2.401 Dillon Varone (1): drm/amd/display: Add dcn42b project id Harry Wentland (2): drm/amd/display: enable shaper when programming 3DLUT drm/amd/display: log MCM shaper and 3D LUT mode in the DTN log Ilya Bakoulin (1): drm/amd/display: Add HDMI RR and SCDC skips Ivan Lipski (1): drm/amd/display: Send HDMI VRR metadata in VTEM info packet slot Joshua Aberback (1): drm/amd/display: Revert "avoid to write signal specific for tmds" Martin Tsai (1): drm/amd/display: allow skipping link bandwidth clear Rafal Ostrowski (2): drm/amd/display: Refactor DMUB fast lock sequencing drm/amd/display: Prepare DSC configuration before BLS execution Relja Vojvodic (1): drm/amd/display: Update link training no timeout behaviour on HDMI Sridevi Arvindekar (1): drm/amd/display: Handle virtual link encoder .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 + .../display/amdgpu_dm/amdgpu_dm_freesync.c | 26 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 101 +--- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 522 ++++++++++++------ .../drm/amd/display/dc/core/dc_link_exports.c | 5 + .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_stream.c | 36 +- drivers/gpu/drm/amd/display/dc/dc.h | 8 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 1 + drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 2 + .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 12 +- .../dc/dml2_0/dml21/inc/dml_top_types.h | 1 + .../dml21/src/dml2_cga/dml2_cga_factory.c | 1 + .../dml21/src/dml2_core/dml2_core_factory.c | 1 + .../dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 1 + .../dml21/src/dml2_mcg/dml2_mcg_factory.c | 1 + .../dml21/src/dml2_pmo/dml2_pmo_factory.c | 1 + .../dml21/src/dml2_top/dml2_top_interfaces.c | 1 + .../dml2_utm_soc_bb/dml2_utm_soc_bb_factory.c | 1 + .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 48 +- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 13 +- .../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 1 + .../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 34 +- .../amd/display/dc/dsc/dcn401/dcn401_dsc.h | 5 +- .../drm/amd/display/dc/dsc/dcn60/dcn60_dsc.c | 41 +- .../drm/amd/display/dc/dsc/dcn60/dcn60_dsc.h | 3 +- drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 3 +- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 17 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 11 +- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 14 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 32 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 +- .../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 99 ++-- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 12 +- .../amd/display/dc/hwss/dcn35/dcn35_init.c | 2 + .../amd/display/dc/hwss/dcn351/dcn351_init.c | 2 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 67 +-- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_init.c | 2 +- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 16 +- .../amd/display/dc/hwss/dcn42/dcn42_hwseq.h | 2 +- .../amd/display/dc/hwss/dcn42/dcn42_init.c | 2 +- .../amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 11 +- .../amd/display/dc/hwss/dcn60/dcn60_init.c | 2 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 108 ++-- .../drm/amd/display/dc/link/link_detection.c | 4 +- .../gpu/drm/amd/display/dc/link/link_dpms.c | 17 +- .../amd/display/dc/link/protocols/link_ddc.c | 17 +- .../amd/display/dc/link/protocols/link_ddc.h | 1 - .../dc/link/protocols/link_dp_training.c | 20 +- .../display/dc/link/protocols/link_hdmi_frl.c | 12 +- .../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 18 +- .../dcn60/dcn60_soc_and_ip_translator.c | 39 +- .../amd/display/include/link_service_types.h | 1 + .../amd/display/modules/power/power_replay.c | 6 +- 59 files changed, 853 insertions(+), 563 deletions(-) -- 2.34.1