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Fri, 2 Oct 2026 14:33:04 -0500 From: To: CC: Harry Wentland , Leo Li , Roman Li , Wayne Lin , Tom Chung , Fangzhi Zuo , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Aric Cyr , Josip Pavic Subject: [PATCH 03/17] drm/amd/display: only reprogram DRR when v_total values change Date: Fri, 2 Oct 2026 15:32:26 -0400 Message-ID: <20261002193240.3441018-4-Roman.Li@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261002193240.3441018-1-Roman.Li@amd.com> References: <20261002193240.3441018-1-Roman.Li@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|CH3PR12MB9220:EE_ X-MS-Office365-Filtering-Correlation-Id: df62c069-0f1b-4776-4100-08df20bbfec5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|36860700016|23010399003|10067099003|18002099003|22082099003|11063799006|56012099006|5023799004|6133799003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IgDUhIcCDPbU18XBbY3/d54UMZATz2rPyDt3gD9OFxXjhrHkMq9fhw3BwLxPrgiaEkUX+KkR1Y7peIIHtu50UsSXMXgzsVQs0N+pc62oBfLoNON0jbrxZZuEgGcnnp01cj3kIZoIBC00n0BzRkeVa0PXjZyAKWt4Rhl7/pwJHS0IFUPkx35dOLmQddRdLOX9WxMK0+dPmHZVsXVFqDOJ1fRQy6W05UFtPvPxckXKopX3a5ZZwA4IhvKC/0FBVIkowNApuKVzpADcm6Ohb1owkA86MDurYxsHfjVGIHnfnlwOYuOA/f/6bBx13M5Iz6hNnIbPQD3Ae3QO7i9r78sVsYfII2ry9FPOPJu6AgPF4ylY6b//yJ5sod0/gib16mu9agaxXu0dt52/RnvHC++hBMIh+TxWxSN0xC6Qd5XWxZVzGCEtEuCUh/TZg7/bmUXN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2026 19:33:11.4938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df62c069-0f1b-4776-4100-08df20bbfec5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9220 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Aric Cyr [Why] dc_stream_adjust_vmin_vmax() programmed the OTG on every call. FreeSync BTR calls it once per vblank, so identical v_total values were rewritten every frame, each one paying dc_exit_ips_for_hw_access() and, when FAMS is enabled, a blocking DMUB round trip from setup_manual_trigger(). [How] Return early when timing_adjust_pending is clear and every v_total field already matches the request, so hardware is only touched when the values change. stream->adjust is still updated on every path that continues, so a later commit programs the requested values. timing_adjust_pending is the existing "stream->adjust has not reached hardware" marker, so keep it accurate wherever hardware is left untouched: set_drr_and_clear_adjust_pending() now sets it when called with null params, which resets DRR in the OTG during pipe back-end teardown, and the max_v_total overflow path only clears it when set_long_vtotal() runs. Reviewed-by: Josip Pavic Signed-off-by: Aric Cyr Signed-off-by: Roman Li --- drivers/gpu/drm/amd/display/dc/core/dc.c | 24 +++++++++++++++---- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 3 ++- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 17db12fe8022..254c2a9c1b04 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1342,6 +1342,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_crtc_timing_adjust *adjust) { int i; + bool drr_unchanged; /* * Don't adjust DRR while there's bandwidth optimizations pending to @@ -1356,6 +1357,19 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, } } + /* timing_adjust_pending tracks whether stream->adjust still describes the + * OTG, so a cleared flag plus matching values means hw is already current. + */ + drr_unchanged = !stream->adjust.timing_adjust_pending && + stream->adjust.v_total_min == adjust->v_total_min && + stream->adjust.v_total_max == adjust->v_total_max && + stream->adjust.v_total_mid == adjust->v_total_mid && + stream->adjust.v_total_mid_frame_num == adjust->v_total_mid_frame_num && + stream->adjust.allow_otg_v_count_halt == adjust->allow_otg_v_count_halt; + + if (drr_unchanged) + return true; + dc_exit_ips_for_hw_access(dc); stream->adjust.v_total_max = adjust->v_total_max; @@ -1366,11 +1380,13 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, if (dc->caps.max_v_total != 0 && (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { - stream->adjust.timing_adjust_pending = false; - if (adjust->allow_otg_v_count_halt) + if (adjust->allow_otg_v_count_halt) { + stream->adjust.timing_adjust_pending = false; return set_long_vtotal(dc, stream, adjust); - else - return false; + } + /* Nothing reached hw, so stream->adjust no longer describes the OTG. */ + stream->adjust.timing_adjust_pending = true; + return false; } for (i = 0; i < MAX_PIPES; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 21a62ca4c8dc..3d88c5c377fc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -716,7 +716,8 @@ void set_drr_and_clear_adjust_pending( pipe_ctx->stream_res.tg, params); if (stream) - stream->adjust.timing_adjust_pending = false; + /* A null params resets DRR in hw, leaving stream->adjust stale. */ + stream->adjust.timing_adjust_pending = (params == NULL); } void get_fams2_visual_confirm_color( -- 2.34.1