From: kernel test robot <lkp@intel.com>
To: Caden Chien <chih-wei.chien@amd.com>
Cc: oe-kbuild-all@lists.linux.dev, Alex Deucher <alexander.deucher@amd.com>
Subject: [drm-amdgpu:drm-amdgpu-next 68/175] drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c:138:27: sparse: sparse: cast to restricted __le32
Date: Fri, 02 Oct 2026 20:45:44 +0200 [thread overview]
Message-ID: <202610022032.6A96GbFc-lkp@intel.com> (raw)
tree: https://gitlab.freedesktop.org/drm/amdgpu/kernel drm-amdgpu-next
head: 41505ac433cc4c5179deee8860d197b04f6d1c1d
commit: 99587803152eaac444591b852394e20e665a32fd [68/175] drm/amdgpu/vpe: add vpe v3.0.0 support
config: microblaze-randconfig-r2309-20261002 (https://download.01.org/0day-ci/archive/20261002/202610022032.6A96GbFc-lkp@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 8.5.0
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261002/202610022032.6A96GbFc-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610022032.6A96GbFc-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c:138:27: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c:139:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c:141:27: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c:142:25: sparse: sparse: cast to restricted __le32
--
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:247:32: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:248:37: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:257:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:257:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:257:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:263:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:263:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:263:25: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:670:21: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:818:21: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:880:16: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:1019:27: sparse: sparse: symbol 'vpe_ip_funcs' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:1032:27: sparse: sparse: symbol 'vpe2_ip_funcs' was not declared. Should it be static?
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c:1045:27: sparse: sparse: symbol 'vpe3_ip_funcs' was not declared. Should it be static?
vim +138 drivers/gpu/drm/amd/amdgpu/vpe_v3_0.c
59
60 static int vpe_v3_0_load_microcode(struct amdgpu_vpe *vpe)
61 {
62 struct amdgpu_device *adev = vpe->ring.adev;
63 const struct vpe_firmware_header_v1_0 *vpe_hdr;
64 const __le32 *data;
65 uint32_t ucode_offset[2], ucode_size[2], size_dw, ret;
66 uint32_t f32_offset, f32_cntl, reg_data;
67
68 ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));
69 ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);
70 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret);
71
72 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2));
73 reg_data = REG_SET_FIELD(reg_data, VPEC_CNTL2, IB_FIFO_WATERMARK, 1);
74 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data);
75
76 if (amdgpu_vpe_configure_dpm(vpe))
77 dev_warn(adev->dev, "VPE DPM not enabled.\n");
78
79 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
80
81 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);
82 f32_cntl = RREG32(f32_offset);
83 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);
84 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);
85
86 adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
87 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
88
89 return amdgpu_vpe_psp_update_sram(adev);
90 }
91
92 /* Halt and Check F32 cleaness */
93 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);
94 f32_cntl = RREG32(f32_offset);
95 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1);
96 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 1);
97 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 1);
98 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 1);
99 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);
100
101 f32_cntl = RREG32(f32_offset);
102 if (!REG_GET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT)) {
103 dev_err(adev->dev, "VPEC is not halted");
104 return -EBUSY;
105 }
106
107 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 0);
108 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 0);
109 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);
110
111 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM));
112 if (reg_data) {
113 dev_err(adev->dev, "VPE FW checksum 0 not clean");
114 return -EBUSY;
115 }
116 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM));
117 if (reg_data) {
118 dev_err(adev->dev, "VPE FW checksum 1 not clean");
119 return -EBUSY;
120 }
121
122 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2));
123 if (REG_GET_FIELD(reg_data, VPEC_STATUS2, TH0F32_INSTR_PTR)) {
124 dev_err(adev->dev, "VPE FW initial status not clean");
125 return -EBUSY;
126 }
127
128 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6));
129 if (REG_GET_FIELD(reg_data, VPEC_STATUS6, TH1F32_INSTR_PTR)) {
130 dev_err(adev->dev, "VPE FW initial status not clean");
131 return -EBUSY;
132 }
133 /* end of F32 cleaness check */
134
135 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
136
137 /* Thread 0(command thread) ucode offset/size */
> 138 ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes);
139 ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes);
140 /* Thread 1(control thread) ucode offset/size */
141 ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset);
142 ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes);
143
144 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));
145 reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 0);
146 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);
147
148 for (int j = 0; j < vpe->num_instances; j++) {
149 for (int i = 0; i < 2; i++) {
150 if (i > 0)
151 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);
152 else
153 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);
154
155 data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);
156 size_dw = ucode_size[i] / sizeof(__le32);
157
158 while (size_dw--) {
159 if (amdgpu_emu_mode && size_dw % 500 == 0)
160 msleep(1);
161 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));
162 }
163 }
164 }
165
166 reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL));
167 reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 1);
168 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data);
169
170 /* Unhalt F32 */
171 f32_cntl = RREG32(f32_offset);
172 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);
173 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);
174 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl);
175
176 return 0;
177 }
178
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2026-10-02 18:46 UTC|newest]
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