drivers/clk/berlin/sl261x-pll.c:104 sl261x_pll_register() warn: variable dereferenced before check 'dev' (see line 97)

[kernel test robot <lkp@intel.com>]

Unfiltered warning: this smatch report is sent as-is and has not been
reviewed for false positives, so please treat it with due skepticism.

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
TO: Jisheng Zhang <jszhang@kernel.org>
CC: 0day robot <lkp@intel.com>

tree:   https://github.com/intel-lab-lkp/linux/commits/Jisheng-Zhang/dt-bindings-serial-snps-dw-apb-uart-Add-Synaptics-sl261x-uart/20260929-141358
head:   66f26b6f0baa133e1c8c3a8afb0ef81b5001f027
commit: 03cf77522edc07004a0c25816d9f56083b2049e7 clk: berlin: add Synaptics SL261X SoC clocks and plls
date:   5 days ago
:::::: branch date: 5 days ago
:::::: commit date: 5 days ago
config: arm64-randconfig-r2200-20261003 (https://download.01.org/0day-ci/archive/20261004/202610040708.FiQ4iMQR-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 16.1.0
smatch: v0.5.0-9187-g5189e3fb

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202610040708.FiQ4iMQR-lkp@intel.com/

smatch warnings:
drivers/clk/berlin/sl261x-pll.c:104 sl261x_pll_register() warn: variable dereferenced before check 'dev' (see line 97)

vim +/dev +104 drivers/clk/berlin/sl261x-pll.c

03cf77522edc07 Jisheng Zhang 2026-09-29   93  
03cf77522edc07 Jisheng Zhang 2026-09-29   94  int sl261x_pll_register(struct device *dev, void __iomem *ctrl,
03cf77522edc07 Jisheng Zhang 2026-09-29   95  			const char *out, const char *outf)
03cf77522edc07 Jisheng Zhang 2026-09-29   96  {
03cf77522edc07 Jisheng Zhang 2026-09-29  @97  	struct device_node *np = dev->of_node;
03cf77522edc07 Jisheng Zhang 2026-09-29   98  	struct clk_parent_data parent = {};
03cf77522edc07 Jisheng Zhang 2026-09-29   99  	struct clk_init_data init = {};
03cf77522edc07 Jisheng Zhang 2026-09-29  100  	struct sl261x_pll *pll;
03cf77522edc07 Jisheng Zhang 2026-09-29  101  	struct clk *input;
03cf77522edc07 Jisheng Zhang 2026-09-29  102  	int ret;
03cf77522edc07 Jisheng Zhang 2026-09-29  103  
03cf77522edc07 Jisheng Zhang 2026-09-29 @104  	if (!dev || !ctrl || !out || !outf)
03cf77522edc07 Jisheng Zhang 2026-09-29  105  		return -EINVAL;
03cf77522edc07 Jisheng Zhang 2026-09-29  106  
03cf77522edc07 Jisheng Zhang 2026-09-29  107  	input = of_clk_get(np, 0);
03cf77522edc07 Jisheng Zhang 2026-09-29  108  	if (IS_ERR(input))
03cf77522edc07 Jisheng Zhang 2026-09-29  109  		return dev_err_probe(dev, PTR_ERR(input),
03cf77522edc07 Jisheng Zhang 2026-09-29  110  				     "failed to get PLL reference clock\n");
03cf77522edc07 Jisheng Zhang 2026-09-29  111  	parent.hw = __clk_get_hw(input);
03cf77522edc07 Jisheng Zhang 2026-09-29  112  	ret = devm_add_action_or_reset(dev, sl261x_pll_put_clk, input);
03cf77522edc07 Jisheng Zhang 2026-09-29  113  	if (ret)
03cf77522edc07 Jisheng Zhang 2026-09-29  114  		return ret;
03cf77522edc07 Jisheng Zhang 2026-09-29  115  
03cf77522edc07 Jisheng Zhang 2026-09-29  116  	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
03cf77522edc07 Jisheng Zhang 2026-09-29  117  	if (!pll)
03cf77522edc07 Jisheng Zhang 2026-09-29  118  		return -ENOMEM;
03cf77522edc07 Jisheng Zhang 2026-09-29  119  	pll->ctrl = ctrl;
03cf77522edc07 Jisheng Zhang 2026-09-29  120  
03cf77522edc07 Jisheng Zhang 2026-09-29  121  	init.name = out;
03cf77522edc07 Jisheng Zhang 2026-09-29  122  	init.ops = &sl261x_pllout_ops;
03cf77522edc07 Jisheng Zhang 2026-09-29  123  	init.parent_data = &parent;
03cf77522edc07 Jisheng Zhang 2026-09-29  124  	init.num_parents = 1;
03cf77522edc07 Jisheng Zhang 2026-09-29  125  	init.flags = CLK_GET_RATE_NOCACHE;
03cf77522edc07 Jisheng Zhang 2026-09-29  126  	pll->pllout.init = &init;
03cf77522edc07 Jisheng Zhang 2026-09-29  127  
03cf77522edc07 Jisheng Zhang 2026-09-29  128  	ret = devm_clk_hw_register(dev, &pll->pllout);
03cf77522edc07 Jisheng Zhang 2026-09-29  129  	if (ret)
03cf77522edc07 Jisheng Zhang 2026-09-29  130  		return dev_err_probe(dev, ret, "failed to register pllout\n");
03cf77522edc07 Jisheng Zhang 2026-09-29  131  
03cf77522edc07 Jisheng Zhang 2026-09-29  132  	init.name = outf;
03cf77522edc07 Jisheng Zhang 2026-09-29  133  	init.ops = &sl261x_plloutf_ops;
03cf77522edc07 Jisheng Zhang 2026-09-29  134  	pll->plloutf.init = &init;
03cf77522edc07 Jisheng Zhang 2026-09-29  135  
03cf77522edc07 Jisheng Zhang 2026-09-29  136  	ret = devm_clk_hw_register(dev, &pll->plloutf);
03cf77522edc07 Jisheng Zhang 2026-09-29  137  	if (ret)
03cf77522edc07 Jisheng Zhang 2026-09-29  138  		return dev_err_probe(dev, ret, "failed to register plloutf\n");
03cf77522edc07 Jisheng Zhang 2026-09-29  139  
03cf77522edc07 Jisheng Zhang 2026-09-29  140  	return 0;
03cf77522edc07 Jisheng Zhang 2026-09-29  141  }
03cf77522edc07 Jisheng Zhang 2026-09-29  142  EXPORT_SYMBOL_GPL(sl261x_pll_register);
03cf77522edc07 Jisheng Zhang 2026-09-29  143  

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