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Mon, 5 Oct 2026 02:04:30 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?C=E9dric_Le_Goater?= Subject: [PATCH v2 1/2] hw/arm/aspeed: Sort device IDs alphabetically Thread-Topic: [PATCH v2 1/2] hw/arm/aspeed: Sort device IDs alphabetically Thread-Index: AQHdVG3b6Zq/MRhWHEWGITqjeCkPUg== Date: Mon, 5 Oct 2026 02:04:29 +0000 Message-ID: <20261005020428.3496039-2-jamin_lin@aspeedtech.com> References: <20261005020428.3496039-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261005020428.3496039-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|TY0PR06MB5833:EE_ x-ms-office365-filtering-correlation-id: 68cb8204-f31f-4626-c478-08df2284fdea x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_75_100=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The ASPEED device ID enum has grown over time without a consistent=0A= ordering rule. This makes it difficult to determine where new device=0A= IDs should be added and reduces readability and maintainability as=0A= more devices are introduced.=0A= =0A= Sort the device IDs alphabetically to provide a consistent ordering=0A= rule. Keep related numbered devices together, such as SPI0, SPI1 and=0A= SPI2.=0A= =0A= No functional change.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: C=E9dric Le Goater =0A= ---=0A= include/hw/arm/aspeed_soc.h | 176 ++++++++++++++++++------------------=0A= 1 file changed, 88 insertions(+), 88 deletions(-)=0A= =0A= diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h=0A= index 38226d9b80..a110385743 100644=0A= --- a/include/hw/arm/aspeed_soc.h=0A= +++ b/include/hw/arm/aspeed_soc.h=0A= @@ -195,64 +195,56 @@ struct AspeedSoCClass {=0A= };=0A= =0A= enum {=0A= - ASPEED_DEV_VBOOTROM,=0A= - ASPEED_DEV_SPI_BOOT,=0A= - ASPEED_DEV_IOMEM,=0A= - ASPEED_DEV_IOMEM0,=0A= - ASPEED_DEV_IOMEM1,=0A= - ASPEED_DEV_UART0,=0A= - ASPEED_DEV_UART1,=0A= - ASPEED_DEV_UART2,=0A= - ASPEED_DEV_UART3,=0A= - ASPEED_DEV_UART4,=0A= - ASPEED_DEV_UART5,=0A= - ASPEED_DEV_UART6,=0A= - ASPEED_DEV_UART7,=0A= - ASPEED_DEV_UART8,=0A= - ASPEED_DEV_UART9,=0A= - ASPEED_DEV_UART10,=0A= - ASPEED_DEV_UART11,=0A= - ASPEED_DEV_UART12,=0A= - ASPEED_DEV_UART13,=0A= - ASPEED_DEV_VUART,=0A= - ASPEED_DEV_FMC,=0A= - ASPEED_DEV_SPI0,=0A= - ASPEED_DEV_SPI1,=0A= - ASPEED_DEV_SPI2,=0A= + ASPEED_DEV_ACRY,=0A= + ASPEED_DEV_ADC,=0A= + ASPEED_DEV_DP,=0A= + ASPEED_DEV_DPMCU,=0A= ASPEED_DEV_EHCI1,=0A= ASPEED_DEV_EHCI2,=0A= ASPEED_DEV_EHCI3,=0A= ASPEED_DEV_EHCI4,=0A= - ASPEED_DEV_VIC,=0A= - ASPEED_DEV_INTC,=0A= - ASPEED_DEV_INTCIO,=0A= - ASPEED_DEV_SDMC,=0A= - ASPEED_DEV_SCU,=0A= - ASPEED_DEV_ADC,=0A= - ASPEED_DEV_SBC,=0A= + ASPEED_DEV_EMMC,=0A= ASPEED_DEV_EMMC_BC,=0A= - ASPEED_DEV_VIDEO,=0A= - ASPEED_DEV_SRAM0,=0A= - ASPEED_DEV_SRAM1,=0A= - ASPEED_DEV_SDHCI,=0A= + ASPEED_DEV_ESPI,=0A= + ASPEED_DEV_ETH1,=0A= + ASPEED_DEV_ETH2,=0A= + ASPEED_DEV_ETH3,=0A= + ASPEED_DEV_ETH4,=0A= + ASPEED_DEV_FMC,=0A= + ASPEED_DEV_FSI1,=0A= + ASPEED_DEV_FSI2,=0A= ASPEED_DEV_GPIO,=0A= ASPEED_DEV_GPIO_1_8V,=0A= - ASPEED_DEV_SGPIOM0,=0A= - ASPEED_DEV_SGPIOM1,=0A= - ASPEED_DEV_RTC,=0A= - ASPEED_DEV_TIMER1,=0A= - ASPEED_DEV_TIMER2,=0A= - ASPEED_DEV_TIMER3,=0A= - ASPEED_DEV_TIMER4,=0A= - ASPEED_DEV_TIMER5,=0A= - ASPEED_DEV_TIMER6,=0A= - ASPEED_DEV_TIMER7,=0A= - ASPEED_DEV_TIMER8,=0A= - ASPEED_DEV_WDT,=0A= - ASPEED_DEV_PWM,=0A= - ASPEED_DEV_LPC,=0A= - ASPEED_DEV_IBT,=0A= + ASPEED_DEV_HACE,=0A= ASPEED_DEV_I2C,=0A= + ASPEED_DEV_I3C,=0A= + ASPEED_DEV_IBT,=0A= + ASPEED_DEV_INTC,=0A= + ASPEED_DEV_INTCIO,=0A= + ASPEED_DEV_IOMEM,=0A= + ASPEED_DEV_IOMEM0,=0A= + ASPEED_DEV_IOMEM1,=0A= + ASPEED_DEV_IOEXP0_I2C,=0A= + ASPEED_DEV_IOEXP1_I2C,=0A= + ASPEED_DEV_IOEXP0_I3C,=0A= + ASPEED_DEV_IOEXP1_I3C,=0A= + ASPEED_DEV_IOEXP0_INTCIO,=0A= + ASPEED_DEV_IOEXP1_INTCIO,=0A= + ASPEED_DEV_IPC0,=0A= + ASPEED_DEV_IPC1,=0A= + ASPEED_DEV_JTAG0,=0A= + ASPEED_DEV_JTAG1,=0A= + ASPEED_DEV_KCS,=0A= + ASPEED_DEV_LPC,=0A= + ASPEED_DEV_LTPI_CTRL1,=0A= + ASPEED_DEV_LTPI_CTRL2,=0A= + ASPEED_DEV_LTPI_IO0,=0A= + ASPEED_DEV_LTPI_IO1,=0A= + ASPEED_DEV_MII1,=0A= + ASPEED_DEV_MII2,=0A= + ASPEED_DEV_MII3,=0A= + ASPEED_DEV_MII4,=0A= + ASPEED_DEV_OTP,=0A= ASPEED_DEV_PCIE0,=0A= ASPEED_DEV_PCIE1,=0A= ASPEED_DEV_PCIE2,=0A= @@ -263,49 +255,57 @@ enum {=0A= ASPEED_DEV_PCIE_MMIO1,=0A= ASPEED_DEV_PCIE_MMIO2,=0A= ASPEED_DEV_PECI,=0A= - ASPEED_DEV_ETH1,=0A= - ASPEED_DEV_ETH2,=0A= - ASPEED_DEV_ETH3,=0A= - ASPEED_DEV_ETH4,=0A= - ASPEED_DEV_MII1,=0A= - ASPEED_DEV_MII2,=0A= - ASPEED_DEV_MII3,=0A= - ASPEED_DEV_MII4,=0A= - ASPEED_DEV_SDRAM,=0A= - ASPEED_DEV_XDMA,=0A= - ASPEED_DEV_EMMC,=0A= - ASPEED_DEV_KCS,=0A= - ASPEED_DEV_HACE,=0A= - ASPEED_DEV_ACRY,=0A= - ASPEED_DEV_DPMCU,=0A= - ASPEED_DEV_DP,=0A= - ASPEED_DEV_I3C,=0A= - ASPEED_DEV_ESPI,=0A= - ASPEED_DEV_UDC,=0A= - ASPEED_DEV_JTAG0,=0A= - ASPEED_DEV_JTAG1,=0A= - ASPEED_DEV_FSI1,=0A= - ASPEED_DEV_FSI2,=0A= + ASPEED_DEV_PRIC0,=0A= + ASPEED_DEV_PRIC1,=0A= + ASPEED_DEV_PWM,=0A= + ASPEED_DEV_RTC,=0A= + ASPEED_DEV_SBC,=0A= + ASPEED_DEV_SCU,=0A= ASPEED_DEV_SCUIO,=0A= + ASPEED_DEV_SDHCI,=0A= + ASPEED_DEV_SDMC,=0A= + ASPEED_DEV_SDRAM,=0A= + ASPEED_DEV_SGPIOM0,=0A= + ASPEED_DEV_SGPIOM1,=0A= ASPEED_DEV_SLI,=0A= ASPEED_DEV_SLIIO,=0A= + ASPEED_DEV_SPI_BOOT,=0A= + ASPEED_DEV_SPI0,=0A= + ASPEED_DEV_SPI1,=0A= + ASPEED_DEV_SPI2,=0A= + ASPEED_DEV_SRAM0,=0A= + ASPEED_DEV_SRAM1,=0A= + ASPEED_DEV_TIMER1,=0A= + ASPEED_DEV_TIMER2,=0A= + ASPEED_DEV_TIMER3,=0A= + ASPEED_DEV_TIMER4,=0A= + ASPEED_DEV_TIMER5,=0A= + ASPEED_DEV_TIMER6,=0A= + ASPEED_DEV_TIMER7,=0A= + ASPEED_DEV_TIMER8,=0A= + ASPEED_DEV_UART0,=0A= + ASPEED_DEV_UART1,=0A= + ASPEED_DEV_UART2,=0A= + ASPEED_DEV_UART3,=0A= + ASPEED_DEV_UART4,=0A= + ASPEED_DEV_UART5,=0A= + ASPEED_DEV_UART6,=0A= + ASPEED_DEV_UART7,=0A= + ASPEED_DEV_UART8,=0A= + ASPEED_DEV_UART9,=0A= + ASPEED_DEV_UART10,=0A= + ASPEED_DEV_UART11,=0A= + ASPEED_DEV_UART12,=0A= + ASPEED_DEV_UART13,=0A= + ASPEED_DEV_UDC,=0A= + ASPEED_DEV_VBOOTROM,=0A= + ASPEED_DEV_VIC,=0A= + ASPEED_DEV_VIDEO,=0A= + ASPEED_DEV_VUART,=0A= + ASPEED_DEV_WDT,=0A= + ASPEED_DEV_XDMA,=0A= ASPEED_GIC_DIST,=0A= ASPEED_GIC_REDIST,=0A= - ASPEED_DEV_IPC0,=0A= - ASPEED_DEV_IPC1,=0A= - ASPEED_DEV_LTPI_CTRL1,=0A= - ASPEED_DEV_LTPI_CTRL2,=0A= - ASPEED_DEV_LTPI_IO0,=0A= - ASPEED_DEV_LTPI_IO1,=0A= - ASPEED_DEV_IOEXP0_I2C,=0A= - ASPEED_DEV_IOEXP1_I2C,=0A= - ASPEED_DEV_IOEXP0_INTCIO,=0A= - ASPEED_DEV_IOEXP1_INTCIO,=0A= - ASPEED_DEV_IOEXP0_I3C,=0A= - ASPEED_DEV_IOEXP1_I3C,=0A= - ASPEED_DEV_PRIC0,=0A= - ASPEED_DEV_PRIC1,=0A= - ASPEED_DEV_OTP,=0A= };=0A= =0A= const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);=0A= -- =0A= 2.43.0=0A=