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Mon, 5 Oct 2026 06:44:28 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 05/11] hw/usb/aspeed-udc: Store the EP_DMA_STS write first Thread-Topic: [PATCH v2 05/11] hw/usb/aspeed-udc: Store the EP_DMA_STS write first Thread-Index: AQHdVJT2hZZmdBDzmEi5HlFZvk7EQw== Date: Mon, 5 Oct 2026 06:44:25 +0000 Message-ID: <20261005064418.3060881-6-jamin_lin@aspeedtech.com> References: <20261005064418.3060881-1-jamin_lin@aspeedtech.com> In-Reply-To: <20261005064418.3060881-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SEZPR06MB7362:EE_|SI6PR06MB7166:EE_ x-ms-office365-filtering-correlation-id: 446b9b79-9e50-4648-218a-08df22ac1a2d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The other helpers run after EP_DMA_STS is written. The descriptor mode=0A= kick did not: it had to run before the write, because it stored the=0A= value itself.=0A= =0A= Write the register first in every case, then call the helper. The order=0A= is now the same everywhere, so a later change cannot go wrong on it,=0A= and the code is easier to maintain.=0A= =0A= No functional change.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/usb/aspeed-udc.c | 19 +++++++++++--------=0A= 1 file changed, 11 insertions(+), 8 deletions(-)=0A= =0A= diff --git a/hw/usb/aspeed-udc.c b/hw/usb/aspeed-udc.c=0A= index b43f077c2d..4572914e16 100644=0A= --- a/hw/usb/aspeed-udc.c=0A= +++ b/hw/usb/aspeed-udc.c=0A= @@ -619,12 +619,13 @@ static AspeedUDCXferResult aspeed_udc_ep_xfer_out_sin= gle(AspeedUDCState *s,=0A= * If the request needs more data than was queued, keep it parked and wait= for=0A= * the next kick.=0A= */=0A= -static void aspeed_udc_ep_in_kick_desc(AspeedUDCState *s, int ep, uint32_t= val)=0A= +static void aspeed_udc_ep_in_kick_desc(AspeedUDCState *s, int ep,=0A= + uint32_t old_val)=0A= {=0A= AspeedUDCEP *e =3D &s->ep[ep];=0A= - uint32_t cur_rptr =3D FIELD_EX32(e->regs[R_EP_DMA_STS], EP_DMA_STS, RP= TR);=0A= - uint32_t new_rptr =3D FIELD_EX32(val, EP_DMA_STS, RPTR);=0A= - uint32_t new_wptr =3D FIELD_EX32(val, EP_DMA_STS, WPTR);=0A= + uint32_t new_rptr =3D FIELD_EX32(e->regs[R_EP_DMA_STS], EP_DMA_STS, RP= TR);=0A= + uint32_t new_wptr =3D FIELD_EX32(e->regs[R_EP_DMA_STS], EP_DMA_STS, WP= TR);=0A= + uint32_t cur_rptr =3D FIELD_EX32(old_val, EP_DMA_STS, RPTR);=0A= USBPacket *p =3D e->pkt;=0A= =0A= /*=0A= @@ -641,8 +642,9 @@ static void aspeed_udc_ep_in_kick_desc(AspeedUDCState *= s, int ep, uint32_t val)=0A= cur_rptr =3D new_rptr;=0A= e->desc_off =3D 0;=0A= }=0A= - /* store the guest's write, but keep our own read pointer */=0A= - e->regs[R_EP_DMA_STS] =3D FIELD_DP32(val, EP_DMA_STS, RPTR, cur_rptr);= =0A= + /* keep our own read pointer */=0A= + e->regs[R_EP_DMA_STS] =3D FIELD_DP32(e->regs[R_EP_DMA_STS], EP_DMA_STS= ,=0A= + RPTR, cur_rptr);=0A= =0A= /* nothing to do unless an IN packet is waiting and the ring has data = */=0A= if (!p || cur_rptr =3D=3D new_wptr) {=0A= @@ -715,6 +717,7 @@ static void aspeed_udc_ep_write(void *opaque, hwaddr of= fset, uint64_t data,=0A= AspeedUDCEP *e =3D opaque;=0A= AspeedUDCState *s =3D container_of(e - e->index, AspeedUDCState, ep[0]= );=0A= uint32_t reg =3D offset >> 2;=0A= + uint32_t old_val =3D e->regs[reg];=0A= uint32_t val =3D data;=0A= =0A= trace_aspeed_udc_ep_write(e->index, offset, val);=0A= @@ -725,12 +728,12 @@ static void aspeed_udc_ep_write(void *opaque, hwaddr = offset, uint64_t data,=0A= break;=0A= case R_EP_DMA_STS:=0A= val &=3D 0x77ffffff;=0A= + e->regs[reg] =3D val;=0A= if (FIELD_EX32(e->regs[R_EP_DMA_CTRL], EP_DMA_CTRL, DESC_OP_EN)) {= =0A= /* IN, descriptor-list mode */=0A= - aspeed_udc_ep_in_kick_desc(s, e->index, val);=0A= + aspeed_udc_ep_in_kick_desc(s, e->index, old_val);=0A= } else {=0A= /* OUT, single-stage mode */=0A= - e->regs[reg] =3D val;=0A= aspeed_udc_ep_out_kick_single(s, e->index);=0A= }=0A= break;=0A= -- =0A= 2.43.0=0A=