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Tue, 6 Oct 2026 01:31:41 +0000 Received: from IA3PR12MB923065.namprd12.prod.outlook.com ([fe80::1c83:bf47:4202:50b1]) by IA3PR12MB923065.namprd12.prod.outlook.com ([fe80::1c83:bf47:4202:50b1%5]) with mapi id 15.21.0472.016; Tue, 6 Oct 2026 01:31:41 +0000 From: Tushar Dave To: qemu-devel@nongnu.org Cc: mst@redhat.com, philmd@oss.qualcomm.com, zhao1.liu@intel.com, yishaih@nvidia.com, alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com Subject: [PATCH v2 0/3] pcie/acs: configurable ACS capabilities for root and downstream ports Date: Mon, 5 Oct 2026 20:31:30 -0500 Message-Id: <20261006013133.3457555-1-tdave@nvidia.com> X-Mailer: git-send-email 2.34.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SJ0P220CA0016.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:41b::23) To IA3PR12MB923065.namprd12.prod.outlook.com (2603:10b6:208:627::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA3PR12MB923065:EE_|CY0PR12MB154213:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e02605b-9974-456f-2768-08df23499302 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=tdave@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series adds an 'acs-ctrl' property to PCIe root ports and downstream ports, letting the hypervisor expose a specific PCIe ACS (Access Control Services) configuration to the guest instead of QEMU always advertising every ACS capability the port structurally supports. This matters for P2P (peer-to-peer) topologies such as GPUDirect RDMA, where the actual ACS configuration in effect must match what the host side is doing -- otherwise the guest sees a topology/configuration that doesn't reflect reality, which is undefined behavior and can fail either in software or in hardware. Patch 1 adds the missing ACS capability to xio3130 downstream ports (previously only root ports exposed one), gated behind a new 'x-pcie-acs' property so older machine types can disable it via hw_compat and preserve migration compatibility. Patch 2 introduces the 'acs-ctrl' property itself on both root and downstream ports, so the configured value -- not just the maximal capability set -- is what gets exposed to the guest. Patch 3 makes the ACS Control register read-only to the guest once 'acs-ctrl' has been explicitly configured, so a guest OS doing normal PCIe programming can't silently override the host-configured ACS state. An explicitly configured value of 0 is treated the same as any other configured value (locked), distinct from the property never being set at all (which stays guest-writable, unchanged from current behavior). Changes in v2: - Patch 1: Limit x-pcie-acs to the xio3130 downstream port - Patch 2: Error out when acs-ctrl is set on a port without ACS, reword the commit message and the unsupported-bits error - Patch 3: Make pcie_acs_init() safe for devices that are not PCIe ports, clarify the acs-ctrl property description Link to v1: https://lore.kernel.org/qemu-devel/20260922215008.2554402-1-tdave@nvidia.com/ Tushar Dave (2): xio3130_downstream: Add ACS support for downstream PCIe ports hw/pci: Make ACS Control read-only to guests Yishai Hadas (1): hw/pci: Expose ACS ctrl on Guest as configured by the hypervisor hw/core/machine.c | 1 + hw/pci-bridge/pcie_root_port.c | 14 ++++++- hw/pci-bridge/xio3130_downstream.c | 19 ++++++++++ hw/pci/pcie.c | 61 ++++++++++++++++++++++++++++-- include/hw/pci/pci.h | 3 ++ include/hw/pci/pcie.h | 8 +++- include/hw/pci/pcie_port.h | 2 + 7 files changed, 100 insertions(+), 8 deletions(-) -- 2.34.1