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Tue, 6 Oct 2026 01:31:43 +0000 Received: from IA3PR12MB923065.namprd12.prod.outlook.com ([fe80::1c83:bf47:4202:50b1]) by IA3PR12MB923065.namprd12.prod.outlook.com ([fe80::1c83:bf47:4202:50b1%5]) with mapi id 15.21.0472.016; Tue, 6 Oct 2026 01:31:43 +0000 From: Tushar Dave To: qemu-devel@nongnu.org Cc: mst@redhat.com, philmd@oss.qualcomm.com, zhao1.liu@intel.com, yishaih@nvidia.com, alwilliamson@nvidia.com, jgg@nvidia.com, skolothumtho@nvidia.com Subject: [PATCH v2 1/3] xio3130_downstream: Add ACS support for downstream PCIe ports Date: Mon, 5 Oct 2026 20:31:31 -0500 Message-Id: <20261006013133.3457555-2-tdave@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261006013133.3457555-1-tdave@nvidia.com> References: <20261006013133.3457555-1-tdave@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BY3PR10CA0030.namprd10.prod.outlook.com (2603:10b6:a03:255::35) To IA3PR12MB923065.namprd12.prod.outlook.com (2603:10b6:208:627::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA3PR12MB923065:EE_|CY0PR12MB154213:EE_ X-MS-Office365-Filtering-Correlation-Id: 48baa558-3909-44d1-5efa-08df23499435 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=tdave@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.24, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When a PASID-capable device is added behind the PCIe downstream port, for example, an Nvidia GPU, the PCIe downstream ports must expose ACS capability otherwise PASID won't get enabled. In addition, the other use case is GPUDirect RDMA using Data Direct that must require special ACS controls at the PCIe downstream ports for P2P communication. Gate it behind a new x-pcie-acs property (default on), following the x-pcie-* compat-bit convention (x-pcie-ext-tag/x-pcie-err-unc-mask/ x-pcie-ari-nextfn-1), so older machine types can disable it via hw_compat to preserve migration compatibility. Signed-off-by: Tushar Dave --- hw/core/machine.c | 1 + hw/pci-bridge/xio3130_downstream.c | 9 +++++++++ include/hw/pci/pci.h | 3 +++ 3 files changed, 13 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index d9ac4b419a..b1b3911430 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -43,6 +43,7 @@ GlobalProperty hw_compat_11_1[] = { { "sysbus-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, { "pci-ehci-usb", "x-migrate-fetch-addr-64bit", "off" }, + { "xio3130-downstream", "x-pcie-acs", "off" }, }; const size_t hw_compat_11_1_len = G_N_ELEMENTS(hw_compat_11_1); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 0c3fed3053..6a9df5c174 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -40,6 +40,8 @@ #define XIO3130_SSVID_SSID 0 #define XIO3130_EXP_OFFSET 0x90 #define XIO3130_AER_OFFSET 0x100 +#define XIO3130_ACS_OFFSET \ + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF) static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) @@ -60,6 +62,7 @@ static void xio3130_downstream_reset(DeviceState *qdev) pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); pcie_cap_arifwd_reset(d); + pcie_acs_reset(d); pci_bridge_reset(qdev); } @@ -111,6 +114,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err; } + if (d->cap_present & QEMU_PCIE_CAP_ACS) { + pcie_acs_init(d, XIO3130_ACS_OFFSET); + } + return; err: @@ -137,6 +144,8 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_BIT("x-pcie-acs", PCIDevice, cap_present, + QEMU_PCIE_ACS_BITNR, true), }; static const VMStateDescription vmstate_xio3130_downstream = { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index f2448e941a..dd52b9639e 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -231,6 +231,9 @@ enum { QEMU_PCI_CAP_PM = (1 << QEMU_PCI_CAP_PM_BITNR), #define QEMU_PCI_SKIP_RESET_ON_CPR_BITNR 15 QEMU_PCI_SKIP_RESET_ON_CPR = (1 << QEMU_PCI_SKIP_RESET_ON_CPR_BITNR), + /* PCIe ACS (Access Control Services) extended capability present */ +#define QEMU_PCIE_ACS_BITNR 16 + QEMU_PCIE_CAP_ACS = (1 << QEMU_PCIE_ACS_BITNR), }; typedef struct PCIINTxRoute { -- 2.34.1