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dCBiZDg0NWM5Yjk3YzdiM2IxYzllYzA3ZmVjNmRhYTEyZjliMDc2NmQ1CkF1dGhvcjogVmFyYWRh cmFqYW4gTmFyYXlhbmFuIDx2YXJhZGFyYWphbi5uYXJheWFuYW5Ab3NzLnF1YWxjb21tLmNvbT4K CnBoeTogcWNvbTogc25wcy1mZW10by12MjogQWRkIElQUTk2NTAgc3VwcG9ydAoKQWRkIHRoZSA2 IG5tIFNOUFMgZmVtdG8gVVNCMiBQSFkgY29uZmlndXJhdGlvbiBuZWVkZWQgYnkgSVBROTY1MC4K VGhlIFBIWXMgb24gdGhpcyBTb0MgcmVxdWlyZSBhIGRlZGljYXRlZCBpbml0IHNlcXVlbmNlIGFu ZCBvdmVycmlkZQpwYXJhbWV0ZXJzIGJlZm9yZSB0aGV5IGNhbiBiZSBlbmFibGVkLgoKPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9waHkvcXVhbGNvbW0vcGh5LXFjb20tc25wcy1mZW10by12Mi5jIGIv ZHJpdmVycy9waHkvcXVhbGNvbW0vcGh5LXFjb20tc25wcy1mZW10by12Mi5jCj4gaW5kZXggMmUz N2IzOWRhYmJhYS4uM2VkNDI5MmZjOGMzMCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3BoeS9xdWFs Y29tbS9waHktcWNvbS1zbnBzLWZlbXRvLXYyLmMKPiArKysgYi9kcml2ZXJzL3BoeS9xdWFsY29t bS9waHktcWNvbS1zbnBzLWZlbXRvLXYyLmMKPiBAQCAtMjksMTIgKzI5LDE1IEBACj4gIAo+ICAj ZGVmaW5lIFVTQjJfUEhZX1VTQl9QSFlfVVRNSV9DVFJMNQkJKDB4NTApCj4gICNkZWZpbmUgUE9S CQkJCQlCSVQoMSkKPiArI2RlZmluZSBBVEVSRVNFVAkJCQlCSVQoMCkKPiAgCj4gICNkZWZpbmUg VVNCMl9QSFlfVVNCX1BIWV9IU19QSFlfQ1RSTF9DT01NT04wCSgweDU0KQo+ICAjZGVmaW5lIFNJ RERRCQkJCQlCSVQoMikKPiAgI2RlZmluZSBSRVRFTkFCTEVOCQkJCUJJVCgzKQo+ICAjZGVmaW5l IEZTRUxfTUFTSwkJCQlHRU5NQVNLKDYsIDQpCj4gICNkZWZpbmUgRlNFTF9ERUZBVUxUCQkJCSgw eDMgPDwgNCkKPiArI2RlZmluZSBGU0VMXzI0TUhaCQkJCUZJRUxEX1BSRVBfQ09OU1QoRlNFTF9N QVNLLCAyKQoKW1NldmVyaXR5OiBMb3ddCklzIGl0IHBvc3NpYmxlIHRoaXMgY291bGQgY2F1c2Ug YnVpbGQgZmFpbHVyZXMgb24gYXJjaGl0ZWN0dXJlcyB3aGVyZQpsaW51eC9iaXRmaWVsZC5oIGlz IG5vdCB0cmFuc2l0aXZlbHkgaW5jbHVkZWQ/IFJlbHlpbmcgb24gdHJhbnNpdGl2ZQpoZWFkZXIg aW5jbHVzaW9ucyBtaWdodCBicmVhayB3aGVuIGltcGxpY2l0IGluY2x1ZGUgY2hhaW5zIGRpZmZl ci4KClsgLi4uIF0KCj4gQEAgLTQxOCw2ICs0NDIsMzIgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBw aHlfcmVnX2NvbmZpZyBoc181bm1fcGh5X3Bvc3RfdHVuaW5nW10gPSB7Cj4gIAl7IFVTQjJfUEhZ X1VTQl9QSFlfQ0ZHMCwgVVRNSV9QSFlfQ01OX0NUUkxfT1ZFUlJJREVfRU4sIDAgfSwKPiAgfTsK PiAgCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcGh5X3JlZ19jb25maWcgaHNfNm5tX3BoeV9wcmVf dHVuaW5nW10gPSB7Cj4gKwl7IFVTQjJfUEhZX1VTQl9QSFlfQ0ZHMCwgVVRNSV9QSFlfQ01OX0NU UkxfT1ZFUlJJREVfRU4sIFVUTUlfUEhZX0NNTl9DVFJMX09WRVJSSURFX0VOIH0sCj4gKwl7IFVT QjJfUEhZX1VTQl9QSFlfVVRNSV9DVFJMNSwgUE9SLCBQT1IgfSwKPiArCXsgVVNCMl9QSFlfVVNC X1BIWV9GU0VMX1NFTCwgRlNFTF9TRUwsIEZTRUxfU0VMIH0sCj4gKwl7IFVTQjJfUEhZX1VTQl9Q SFlfSFNfUEhZX0NUUkxfQ09NTU9OMCwgRlNFTF9NQVNLLCBGU0VMXzI0TUhaIH0sCj4gKwl7IFVT QjJfUEhZX1VTQl9QSFlfSFNfUEhZX0NUUkxfQ09NTU9OMSwgUExMQlRVTkUsIFBMTEJUVU5FIH0s Cj4gKwl7IFVTQjJfUEhZX1VTQl9QSFlfUkVGQ0xLX0NUUkwsIFJFRkNMS19TRUxfTUFTSywgUkVG Q0xLX1NFTF9ERUZBVUxUIH0sCj4gKwl7IFVTQjJfUEhZX1VTQl9QSFlfSFNfUEhZX0NUUkxfQ09N TU9OMSwgVkJVU1ZMREVYVFNFTDAsIFZCVVNWTERFWFRTRUwwIH0sCj4gKwl7IFVTQjJfUEhZX1VT Ql9QSFlfSFNfUEhZX0NUUkwxLCBWQlVTVkxERVhUMCwgVkJVU1ZMREVYVDAgfSwKPiArfTsKPiAr Cj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcGh5X3JlZ19jb25maWcgaHNfNm5tX3BoeV9wb3N0X3R1 bmluZ1tdID0gewo+ICsJeyBVU0IyX1BIWV9VU0JfUEhZX0hTX1BIWV9DVFJMX0NPTU1PTjIsIFZS RUdCWVBBU1MsIFZSRUdCWVBBU1MgfSwKPiArCXsgVVNCMl9QSFlfVVNCX1BIWV9VVE1JX0NUUkw1 LCBBVEVSRVNFVCwgMCB9LAo+ICsJeyBVU0IyX1BIWV9VU0JfUEhZX0hTX1BIWV9URVNUMSwgVEVT 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sashiko-reviews@lists.linux.dev To: "Varadarajan Narayanan" Cc: vkoul@kernel.org, devicetree@vger.kernel.org, neil.armstrong@linaro.org, olteanv@gmail.com, robh@kernel.org, linux-phy@lists.infradead.org, conor+dt@kernel.org In-Reply-To: <20261006-phy-v5-6-cbe9330a6449@oss.qualcomm.com> References: <20261006-phy-v5-0-cbe9330a6449@oss.qualcomm.com> <20261006-phy-v5-6-cbe9330a6449@oss.qualcomm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 06 Oct 2026 05:39:53 +0000 Message-Id: <20261006053954.5D9581F000FF@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [Medium] phy: qcom: missing SIDDQ clear in 6nm PHY post-tuning - [Low] build: missing for FIELD_PREP_CONST -- commit bd845c9b97c7b3b1c9ec07fec6daa12f9b0766d5 Author: Varadarajan Narayanan phy: qcom: snps-femto-v2: Add IPQ9650 support Add the 6 nm SNPS femto USB2 PHY configuration needed by IPQ9650. The PHYs on this SoC require a dedicated init sequence and override parameters before they can be enabled. > diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/= qualcomm/phy-qcom-snps-femto-v2.c > index 2e37b39dabbaa..3ed4292fc8c30 100644 > --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c > +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c > @@ -29,12 +29,15 @@ > =20 > #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) > #define POR BIT(1) > +#define ATERESET BIT(0) > =20 > #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) > #define SIDDQ BIT(2) > #define RETENABLEN BIT(3) > #define FSEL_MASK GENMASK(6, 4) > #define FSEL_DEFAULT (0x3 << 4) > +#define FSEL_24MHZ FIELD_PREP_CONST(FSEL_MASK, 2) [Severity: Low] Is it possible this could cause build failures on architectures where linux/bitfield.h is not transitively included? Relying on transitive header inclusions might break when implicit include chains differ. [ ... ] > @@ -418,6 +442,32 @@ static const struct phy_reg_config hs_5nm_phy_post_t= uning[] =3D { > { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, > }; > =20 > +static const struct phy_reg_config hs_6nm_phy_pre_tuning[] =3D { > + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CT= RL_OVERRIDE_EN }, > + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, > + { USB2_PHY_USB_PHY_FSEL_SEL, FSEL_SEL, FSEL_SEL }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, FSEL_24MHZ }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, > + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 = }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, > +}; > + > +static const struct phy_reg_config hs_6nm_phy_post_tuning[] =3D { > + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, > + { USB2_PHY_USB_PHY_UTMI_CTRL5, ATERESET, 0 }, > + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTDATAOUTSEL, 0 }, > + { USB2_PHY_USB_PHY_HS_PHY_TEST1, TESTCLK, 0 }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, VATESTENB_MASK, 0 }, [Severity: Medium] Does this sequence intentionally omit clearing the SIDDQ deep sleep bit? If the analog PHY defaults to deep sleep (SIDDQ=3D1), omitting the clear operation could leave the PHY powered down and non-functional during boot or interface initialization. Looking at hs_5nm_phy_post_tuning(), it explicitly clears the SIDDQ bit: { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 } Could the 6nm hardware behavior identically match the 5nm/7nm and other Synopsys PHYs where SIDDQ defaults to 1, requiring it to be cleared here? > + { USB2_PHY_USB_PHY_HS_PHY_TEST0, TESTDATAIN_MASK, 0 }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, > + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, > + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, > + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, > + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, > + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, > +}; --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20261006-phy-v5-0-c= be9330a6449@oss.qualcomm.com?part=3D6