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[83.28.37.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a17a0fc2e4sm97768435e9.3.2026.10.06.14.49.38 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 06 Oct 2026 14:49:39 -0700 (PDT) Date: Tue, 6 Oct 2026 23:49:35 +0200 From: Michal Pecio To: Paul Menzel Cc: Mathias Nyman , Greg Kroah-Hartman , linux-usb@vger.kernel.org, LKML , linuxppc-dev@lists.ozlabs.org, Benjamin Herrenschmidt Subject: Re: IBM Power S822LC: pci 0021:0d:00.0: xHCI HW did not halt within 32000 usec status = 0x0 Message-ID: <20261006234935.0c40c635.michal.pecio@gmail.com> In-Reply-To: References: <20260506193037.6de9e355.michal.pecio@gmail.com> <69fa1c3f-3ea9-42cb-a49a-7da39f72806e@molgen.mpg.de> <20260512012006.66aeb0c5.michal.pecio@gmail.com> <6106b5b9-17d2-48be-8215-3320f3d1d261@molgen.mpg.de> <20260512102233.290d3665.michal.pecio@gmail.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Tue, 12 May 2026 17:32:09 +0200, Paul Menzel wrote: > As a further data point, adding `ppc_pci_reset_phbs` to the command line= =20 > also gets xhci_hcd to initialize the TI xHCI host controller: >=20 > $ lspci -nn -s 0021:0d:00.0 > 0021:0d:00.0 USB controller [0c03]: Texas Instruments TUSB73x0=20 > SuperSpeed USB 3.0 xHCI Host Controller [104c:8241] (rev 02) >=20 >=20 > [ 14.050249] Issue PHB reset ... > [=E2=80=A6] > [ 19.339822] ehci_hcd: block sizes: qh 144 qtd 96 itd 192 sitd 96 > [ 19.339919] ohci_hcd: block sizes: ed 112 td 96 > [ 19.340538] xhci_hcd 0021:0d:00.0: xHCI Host Controller Hi Paul, Are you still interested in this issue, or happy with your workaround? Maybe both? I have some updates: We learned that the kernel does dodgy things with the FW handoff protocol, particularly with TI chips. This may possibly matter if FW is involved. I could supply patches to test this hypothesis. A suspiciously similar case has been reported here: https://lore.kernel.org/linux-usb/b43b9d21-4134-4e4c-89d8-f867207b125e@linu= x.intel.com/T/ There is a new workaround: PCI device reset before kexec. Weird. > No log `xHCI HW did not halt within 32000 usec status =3D 0x0` (or 0x10=20 > with the other patch). In `arch/powerpc/platforms/powernv/pci-ioda.c`,=20 > reading the comment in `pnv_pci_init_ioda_phb()` suggests, that PHB=20 > should be reset also in the kexec case: >=20 > /* > * If we're running in kdump kernel, the previous kernel never > * shutdown PCI devices correctly. We already got IODA table > * cleaned out. So we have to issue PHB reset to stop all PCI > * transactions from previous kernel. The ppc_pci_reset_phbs > * kernel parameter will force this reset too. Additionally, > * if the IODA reset above failed then use a bigger hammer. > * This can happen if we get a PHB fatal error in very early > * boot. > */ > if (is_kdump_kernel() || pci_reset_phbs || rc) { > pr_info(" Issue PHB reset ...\n"); > pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); > pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); > } >=20 > At least, I=E2=80=99d assume that kdump and kexec are similar, that both = do not=20 > shut down PCI devices? (Commit 361f2a2a1536 (powrpc/powernv: Reset PHB=20 > in kdump kernel) from 2024 adds (some) the code above.) Apparently, we try to shut down PCI devices on kexec, unless loading a crash dump kernel on panic. So as I wrote in the new thread, we already call xhci_halt() before kexec, the xHC should be halted, and for new kernel xhci_halt() should be almost a no-op with guaranteed success. It seems that we are failing to actually halt it, or something (FW?) touches the chip during kexec, or something else is quite weird. Regards, Michal