From: Richard Cheng <icheng@nvidia.com>
To: jic23@kernel.org, dave@stgolabs.net, dave.jiang@intel.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
iweiny@kernel.org, ming.li@zohomail.com, icheng@nvidia.com
Cc: kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com,
kristinc@nvidia.com, linux-cxl@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [RFC PATCH v2 3/3] cxl/test: Exercise explicit Type-2 RAM region creation
Date: Wed, 7 Oct 2026 17:05:39 +0800 [thread overview]
Message-ID: <20261007090540.43817-4-icheng@nvidia.com> (raw)
In-Reply-To: <20261007090540.43817-1-icheng@nvidia.com>
Add a second mock Type-2 accelerator without a FW-provided region.
Register its memdev, try attachment, and explicitly create a 256 MB RAM
region when needed.
Check the returned HPA range and retain the original accelerator on
devm_cxl_probe_mem(). Preserve MANUAL DEVMEM configuration after
disabled reply or failed saved-state restoration.
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
Changelog:
v1 -> v2:
- Use separate registration, creation and attachment APIs
- Request 256 MB from 512 MB capacity
- Preserve DEVMEM config after failed restoration
---
tools/testing/cxl/test/accel.c | 28 +++++++++++++++++++-
tools/testing/cxl/test/cxl.c | 47 +++++++++++++++++++++++++++++-----
2 files changed, 68 insertions(+), 7 deletions(-)
diff --git a/tools/testing/cxl/test/accel.c b/tools/testing/cxl/test/accel.c
index 8e6f4687ca02..83962702145d 100644
--- a/tools/testing/cxl/test/accel.c
+++ b/tools/testing/cxl/test/accel.c
@@ -20,6 +20,7 @@ static int cxl_mock_accel_probe(struct platform_device *pdev)
struct cxl_dev_state *cxlds;
struct cxl_memdev *cxlmd;
struct range mock_range;
+ u64 region_size = pdev->id == 0 ? SZ_512M : SZ_256M;
int rc;
cxl_accel = devm_cxl_dev_state_create(&pdev->dev, CXL_DEVTYPE_DEVMEM,
@@ -35,9 +36,34 @@ static int cxl_mock_accel_probe(struct platform_device *pdev)
if (rc)
return rc;
- cxlmd = devm_cxl_probe_mem(cxlds, &mock_range);
+ /* Keep the firmware-configured accelerator on the legacy API. */
+ if (pdev->id == 0)
+ cxlmd = devm_cxl_probe_mem(cxlds, &mock_range);
+ else
+ cxlmd = devm_cxl_register_mem(cxlds);
if (IS_ERR(cxlmd))
return PTR_ERR(cxlmd);
+
+ if (pdev->id != 0) {
+ rc = devm_cxl_attach_mem_region(cxlmd, &mock_range);
+ if (rc == -ENXIO) {
+ /* The provider chooses to map half its volatile capacity. */
+ rc = devm_cxl_create_ram_region(cxlmd, region_size);
+ if (rc)
+ return rc;
+ rc = devm_cxl_attach_mem_region(cxlmd, &mock_range);
+ }
+ if (rc)
+ return rc;
+ }
+
+ if (mock_range.start > mock_range.end ||
+ range_len(&mock_range) != region_size) {
+ dev_err(dev,
+ "accelerator%d returned invalid HPA range %pra (expected %llu bytes)\n",
+ pdev->id, &mock_range, region_size);
+ return -ERANGE;
+ }
cxl_accel->cxlmd = cxlmd;
dev_dbg(dev, "Probed mock accelerator with range %pra\n", &mock_range);
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 3eb1051b1ee8..4fab2572a1aa 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -29,7 +29,7 @@ static bool mock_zero_size_decoders;
#define NR_CXL_SWITCH_PORTS 2
#define NR_CXL_PORT_DECODERS 8
#define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH)
-#define NR_CXL_TYPE2_ACCEL 1
+#define NR_CXL_TYPE2_ACCEL 2
#define MOCK_AUTO_REGION_SIZE_DEFAULT SZ_512M
static int mock_auto_region_size = MOCK_AUTO_REGION_SIZE_DEFAULT;
@@ -494,7 +494,17 @@ static void cfmws_elc_update(struct acpi_cedt_cfmws *window, int index)
static void update_type2_cfmws(void)
{
+ struct acpi_cedt_cfmws *window = &mock_cedt.cfmws1.cfmws;
+
memcpy(&mock_cedt.cfmws0.cfmws, &type2_cfmws0, sizeof(type2_cfmws0));
+
+ /* Give the unconfigured accelerator its own single-target window. */
+ window->header.length = sizeof(*window) +
+ sizeof(mock_cedt.cfmws1.target[0]);
+ window->interleave_ways = 0;
+ window->restrictions = ACPI_CEDT_CFMWS_RESTRICT_DEVMEM |
+ ACPI_CEDT_CFMWS_RESTRICT_VOLATILE;
+ mock_cedt.cfmws1.target[0] = 1;
}
static int populate_cedt(void)
@@ -1122,6 +1132,7 @@ enum cxld_init_type {
MOCK_DECODER_INIT_SAVED,
MOCK_DECODER_INIT_TYPE3_AUTO,
MOCK_DECODER_INIT_TYPE2_AUTO,
+ MOCK_DECODER_INIT_TYPE2_MANUAL,
};
static enum cxld_init_type get_decoder_init_type(struct cxl_decoder *cxld,
@@ -1131,12 +1142,13 @@ static enum cxld_init_type get_decoder_init_type(struct cxl_decoder *cxld,
{
struct cxl_test_decoder *found_td = cxld_registry_find(cxld);
- if (found_td) {
- *td = found_td;
- return MOCK_DECODER_INIT_SAVED;
- }
+ *td = found_td;
+ if (type2_test && is_endpoint_decoder(&cxld->dev) && pdev->id == 1 &&
+ cxld->id == 0)
+ return MOCK_DECODER_INIT_TYPE2_MANUAL;
- *td = NULL;
+ if (found_td)
+ return MOCK_DECODER_INIT_SAVED;
/*
* The first decoder on the first 2 devices on the first switch
@@ -1170,6 +1182,27 @@ static bool mock_decoder_handle_saved(struct cxl_decoder *cxld, struct cxl_test_
return false;
}
+static bool mock_init_hdm_type2_manual(struct cxl_endpoint_decoder *cxled,
+ struct cxl_test_decoder *td)
+{
+ struct cxl_decoder *cxld = &cxled->cxld;
+
+ if (td) {
+ if (mock_decoder_handle_saved(cxld, td))
+ return true;
+ } else {
+ init_disabled_mock_decoder(cxld);
+ }
+
+ /* Preserve DEVMEM on disabled replay and failed saved-state restore. */
+ cxld->target_type = CXL_DECODER_DEVMEM;
+ cxld->interleave_granularity = CXL_DECODER_MIN_GRANULARITY;
+ if (!td)
+ WARN_ON_ONCE(!cxld_registry_new(cxld));
+
+ return false;
+}
+
static void mock_init_hdm_type2_cxled(struct cxl_endpoint_decoder *cxled,
struct cxl_port *port)
{
@@ -1445,6 +1478,8 @@ static bool mock_init_hdm_decoder(struct cxl_decoder *cxld)
case MOCK_DECODER_INIT_TYPE2_AUTO:
mock_init_hdm_type2_cxled(cxled, port);
return false;
+ case MOCK_DECODER_INIT_TYPE2_MANUAL:
+ return mock_init_hdm_type2_manual(cxled, td);
default:
return false;
}
--
2.43.0
next prev parent reply other threads:[~2026-10-07 9:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-07 9:05 [RFC PATCH v2 0/3] cxl: Provide explicit RAM region creation for Type-2 providers Richard Cheng
2026-10-07 9:05 ` [RFC PATCH v2 1/3] cxl/mem: Separate provider registration from region attachment Richard Cheng
2026-10-07 9:05 ` [RFC PATCH v2 2/3] cxl/mem: Add explicit RAM region creation for providers Richard Cheng
2026-10-07 9:05 ` Richard Cheng [this message]
2026-10-09 18:34 ` [RFC PATCH v2 3/3] cxl/test: Exercise explicit Type-2 RAM region creation Dave Jiang
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