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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48c71d2e2e9sm4434133f8f.46.2026.10.07.02.47.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 07 Oct 2026 02:47:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Stafford Horne Subject: [PATCH 15/27] target/or1k: Register CPUClass::exception_name() handler Date: Wed, 7 Oct 2026 11:45:03 +0200 Message-ID: <20261007094516.75732-16-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com> References: <20261007094516.75732-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfX0x9wf6HLO8z5 OqzNQ5sGDn4b4v91d+jl4gExL+x66MEEijt7bqii6265tWWxCMOD/uQySC5Lnxp/CH0sL41fBVy nljlGLZCPcliAcSlF8hofmR3tFA7CMU= X-Proofpoint-ORIG-GUID: bAeNm7BKlkDoovvloUDpf-euMxZFi2km X-Proofpoint-GUID: bAeNm7BKlkDoovvloUDpf-euMxZFi2km X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfXwmKFD/celtEf bHqz5ECCYmHw1sseCeAQu80KMfmT0VszSzb/Rf3+ru9rxRnUZQ83naf/xx19gyCuBrzvNck+rMK LjJb0G7nsH893KlwdQlR2EircHU+mhrsQ1eJgKZG1MFdew3pMFGHwm9e2XpwH4Frhij87IgtaBQ 3xx4lUbs/K+jvDAmS4Fd9FnbtM9dAOiqNkIGLOpl+ej0aGQGLBkS/J/Q4zLJEWcoEDbkIg+SL7Z f/FvlmAIdIEgkYPvdX7oAG8lPsPZVrynDOk5PjETtjtWvzGMcS8+eg1h/a0auAxAImkMOZfi4Yp vDeyYTK8rOwTTVAf2HC5ZFF8P8gjdBs5jDa/Ic1rz7i8QLsb6vGn1c7YTh2xBMOzee4Tiiy/50I y9da0Gkgi272Z62Rnrm8Vt6HulqpQFNsrfe1mGNohO5QJbnfttpXnDjSqg08jyvNRqKMmlqHZIK mgp4dtgv4jd8xyZa3Qw== X-Authority-Analysis: v=2.4 cv=Af0kjHXG c=1 sm=1 tr=0 ts=6ac6151c cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=slxP8ohElPSaHwuvTCoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070038 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Factor openrisc_excp_name() out of openrisc_cpu_do_interrupt() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve OpenRISC exception codes to names. Signed-off-by: Philippe Mathieu-Daudé --- target/or1k/cpu.h | 2 ++ target/or1k/cpu.c | 1 + target/or1k/exception.c | 24 ++++++++++++++++++++++++ target/or1k/interrupt.c | 19 +------------------ 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/or1k/cpu.h b/target/or1k/cpu.h index fc4387ce7ae..96ed1779fae 100644 --- a/target/or1k/cpu.h +++ b/target/or1k/cpu.h @@ -155,6 +155,8 @@ enum { EXCP_NR, }; +const char *openrisc_excp_name(int excp); + /* Supervisor register */ enum { SR_SM = (1 << 0), diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 66c00c0930c..e15f6bb5e71 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -285,6 +285,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, const void *data) &occ->parent_phases); cc->class_by_name = openrisc_cpu_class_by_name; + cc->exception_name = openrisc_excp_name; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->get_pc = openrisc_cpu_get_pc; diff --git a/target/or1k/exception.c b/target/or1k/exception.c index 0479a069592..388bf6dbab8 100644 --- a/target/or1k/exception.c +++ b/target/or1k/exception.c @@ -22,6 +22,30 @@ #include "cpu.h" #include "exception.h" +const char *openrisc_excp_name(int excp) +{ + static const char * const excp_name[EXCP_NR] = { + [EXCP_RESET] = "RESET", + [EXCP_BUSERR] = "BUSERR (bus error)", + [EXCP_DPF] = "DFP (data protection fault)", + [EXCP_IPF] = "IPF (code protection fault)", + [EXCP_TICK] = "TICK (timer interrupt)", + [EXCP_ALIGN] = "ALIGN", + [EXCP_ILLEGAL] = "ILLEGAL", + [EXCP_INT] = "INT (device interrupt)", + [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", + [EXCP_RANGE] = "RANGE", + [EXCP_SYSCALL] = "SYSCALL", + [EXCP_FPE] = "FPE", + [EXCP_TRAP] = "TRAP", + }; + if (excp < 0 || excp >= ARRAY_SIZE(excp_name) || !excp_name[excp]) { + return "(unknown)"; + } + return excp_name[excp]; +} + G_NORETURN void raise_exception(OpenRISCCPU *cpu, uint32_t excp) { CPUState *cs = CPU(cpu); diff --git a/target/or1k/interrupt.c b/target/or1k/interrupt.c index 6e89157639a..399c98e3881 100644 --- a/target/or1k/interrupt.c +++ b/target/or1k/interrupt.c @@ -66,26 +66,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } if (exception > 0 && exception < EXCP_NR) { - static const char * const int_name[EXCP_NR] = { - [EXCP_RESET] = "RESET", - [EXCP_BUSERR] = "BUSERR (bus error)", - [EXCP_DPF] = "DFP (data protection fault)", - [EXCP_IPF] = "IPF (code protection fault)", - [EXCP_TICK] = "TICK (timer interrupt)", - [EXCP_ALIGN] = "ALIGN", - [EXCP_ILLEGAL] = "ILLEGAL", - [EXCP_INT] = "INT (device interrupt)", - [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", - [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", - [EXCP_RANGE] = "RANGE", - [EXCP_SYSCALL] = "SYSCALL", - [EXCP_FPE] = "FPE", - [EXCP_TRAP] = "TRAP", - }; - qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", cs->cpu_index, - int_name[exception]); + openrisc_excp_name(exception)); hwaddr vect_pc = exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { -- 2.55.0