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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a17f51ba67sm49755585e9.1.2026.10.07.02.47.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 07 Oct 2026 02:47:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org Subject: [PATCH 17/27] target/riscv: Register CPUClass::exception_name() handler Date: Wed, 7 Oct 2026 11:45:05 +0200 Message-ID: <20261007094516.75732-18-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com> References: <20261007094516.75732-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: dOV1ayED76XozHzDPgIHbOU-eWRs7oOQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfX/UhGFdtguRpv msR2vTIXO0GjadYHESdoFTn15J4Jg9bL0LJuaXrDDtkoJIimef0FJgFkkAh18x8afiR4wmibfjY HrV1jS6gQdRNh0VVdFSmYAOs9pH1cmqTMUtTRIvuo0AaQ1zae1nAnWhaHIaTisjXs/WncN/hUIj 02aJGFAKBvWn+nhR/6u7Y2LlSWI1oB4HexVymNlaa7hKT+wc8gUTBPE6i++7LBCFdjo2+ACTjvZ qsJfViGgckBaJdfBSQKJH/TLjndy8MIvjGF5dQAdBM5eF6xXRwJ+NlMUz8Sc+HgDR1UqzNyQ/YF IQ36SOlGedCxC81YfBo2Fv+gvp2HiORfjdyhHsyJXhPJyxnbfagZ/UQQXe30QDi04n5tKLAMZn2 /p/TDIpoTwxAO2hadOX8aBhMuKYAg3GpnApmViLj7Lxtn11QHtigVegSV9ZQDvvl/TkqanKHrYF YbO+5hRO2Tmd7SyZgQA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfX+bw/E4jD9O7z mpg1G3zINki70Ma2rx12kSM44hb4Oe2l7FafjX1wLsPGx6dhvMo9NiMhH7HWyhaoChILqjF8Dlj jeJ3hSwwDukEZueuRnnl/QfVUvjRD/0= X-Proofpoint-GUID: dOV1ayED76XozHzDPgIHbOU-eWRs7oOQ X-Authority-Analysis: v=2.4 cv=NatzRGD4 c=1 sm=1 tr=0 ts=6ac6152b cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=y9j7XMdMAJhvWi9Kj2cA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070038 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Factor riscv_excp_name() and riscv_intr_name() out of riscv_cpu_get_trap_name(). Register riscv_excp_name() as the CPUClass::exception_name() handler, so the common exception logging can resolve RISCV exception codes to names. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 29 ++++++++++++++++++----------- target/riscv/tcg/op_helper.c | 2 +- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd8..61bd0299dde 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -670,6 +670,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); +const char *riscv_excp_name(int excp); #ifndef CONFIG_USER_ONLY void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b9..0f236b0f4b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -394,6 +394,14 @@ static const char * const riscv_excp_names[] = { [RISCV_EXCP_SEMIHOST] = "semihost", }; +const char *riscv_excp_name(int excp) +{ + if ((excp < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[excp]) { + return riscv_excp_names[excp]; + } + return "(unknown)"; +} + static const char * const riscv_intr_names[] = { [IRQ_U_SOFT] = "u_software", [IRQ_S_SOFT] = "s_software", @@ -411,19 +419,17 @@ static const char * const riscv_intr_names[] = { [IRQ_PMU_OVF] = "counter_overflow", }; +static const char *riscv_intr_name(int intr) +{ + if ((intr < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[intr]) { + return riscv_intr_names[intr]; + } + return "(unknown)"; +} + const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) { - if (async) { - if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) { - return riscv_intr_names[cause]; - } - } else { - if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) { - return riscv_excp_names[cause]; - } - } - - return "(unknown)"; + return async ? riscv_intr_name(cause) : riscv_excp_name(cause); } void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) @@ -3039,6 +3045,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; + cc->exception_name = riscv_excp_name; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c index b67c7718db4..ddc603759f2 100644 --- a/target/riscv/tcg/op_helper.c +++ b/target/riscv/tcg/op_helper.c @@ -44,7 +44,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, CPUState *cs = env_cpu(env); trace_riscv_exception(exception, - riscv_cpu_get_trap_name(exception, false), + riscv_excp_name(exception), env->pc); cs->exception_index = exception; -- 2.55.0