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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48c7256434bsm4204084f8f.15.2026.10.07.02.47.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 07 Oct 2026 02:47:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Date: Wed, 7 Oct 2026 11:45:08 +0200 Message-ID: <20261007094516.75732-21-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com> References: <20261007094516.75732-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfX1o4KJ5CtU2yd ck9JIHdNxJtcE4+QcwWe+38r/1RKQxUrMpBh5VbMwE36IrpETLFvyNZAkxzPReP2Aj9M1UxtKlM LIzPzZyn8XFOYhg2tbjex5IFbyQPmwc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAzOCBTYWx0ZWRfX28BH2ipqCnwn PdF0l2RuDjF3DPdxaMXlWXVrTs5gBG1k6oexkt+jaqy7PzqBwIYocqMOnJJdZij7pHBiEVTMQne 4nLG9OFxdpTuAY/H3HcLY1yB4ktZA3rASLQTimKsZZno7fvXdPMNYHEBNcovjRbMrq391OtenjR MKmg5ri/O7hvfepH4Noo+VlXJAKiJb/R04UnNjmKn4a+fvigpkHvcQUlv46hAbQ9tKTZe3RiM/5 HVDq2tIZgLZPJiR7Twtfb4dEI6lCGEnmzBn39iNJKFLFDlOXp3JQ8dvPKkv1yBf8bWRFaih++9m gnRwPQPksL3/F702bRyImj/NiDMT2DUdTIUzl47ZIiooZSIVr8esBKXu6jW6jZFQUnGT4zLdo/Z J894BttaMYEalqqJOQI8FV5bwf3nbeG/e3FTX7M3kMjHarthY1LdiBq1/v8kDvVq8CY1eYL6ca4 c8tZgHvEKwVoNW/9ZCg== X-Proofpoint-ORIG-GUID: 7sgrFZWRnijasUAud4BS5R0hjX4BCXqO X-Authority-Analysis: v=2.4 cv=T5EZ3PKQ c=1 sm=1 tr=0 ts=6ac61540 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=7bFQwIbWrMmj_3m7X6gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: 7sgrFZWRnijasUAud4BS5R0hjX4BCXqO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070038 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Factor rx_exception_name() out of rx_cpu_do_interrupt() and register it as the CPUClass::exception_name() handler, so the common exception logging can resolve RX exception codes to names. Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.h | 1 + target/rx/cpu.c | 1 + target/rx/helper.c | 53 ++++++++++++++++++++++++++++------------------ 3 files changed, 34 insertions(+), 21 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0d9f4898a26..06208380621 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -147,6 +147,7 @@ struct RXCPUClass { #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); +const char *rx_exception_name(int excp); void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9b8473d71cf..bcaf6659ac5 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -245,6 +245,7 @@ static void rx_cpu_class_init(ObjectClass *klass, const void *data) &rcc->parent_phases); cc->class_by_name = rx_cpu_class_by_name; + cc->exception_name = rx_exception_name; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; cc->get_pc = rx_cpu_get_pc; diff --git a/target/rx/helper.c b/target/rx/helper.c index bc76dd28ab3..fd662b1b5b9 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -24,6 +24,37 @@ #include "hw/core/irq.h" #include "qemu/plugin.h" +const char *rx_exception_name(int excp) +{ + const char *name; + + switch (excp) { + case RX_EXCP_PRIVILEGE_VIOLATION: + name = "privilege violation"; + break; + case RX_EXCP_ACCESS: + name = "access exception"; + break; + case RX_EXCP_ILLEGAL_INSTRUCTION: + name = "illegal instruction"; + break; + case RX_EXCP_FPU: + name = "fpu exception"; + break; + case RX_EXCP_NMI: + name = "non-maskable interrupt"; + break; + case RX_EXCP_TRAP_BASE ... RX_EXCP_TRAP_BASE + RX_EXCP_TRAP_COUNT - 1: + name = "unconditional trap"; + break; + default: + name = "unknown exception"; + break; + } + + return name; +} + void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) { if (env->psw_pm == 0) { @@ -79,7 +110,6 @@ void rx_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_irq); } else { uint32_t vec = cs->exception_index; - const char *expname = "unknown exception"; env->isp -= 4; cpu_stl_le_data(env, env->isp, save_psw); @@ -100,27 +130,8 @@ void rx_cpu_do_interrupt(CPUState *cs) qemu_plugin_vcpu_exception_cb(cs, last_pc); } - switch (vec) { - case RX_EXCP_PRIVILEGE_VIOLATION: - expname = "privilege violation"; - break; - case RX_EXCP_ACCESS: - expname = "access exception"; - break; - case RX_EXCP_ILLEGAL_INSTRUCTION: - expname = "illegal instruction"; - break; - case RX_EXCP_FPU: - expname = "fpu exception"; - break; - case RX_EXCP_NMI: - expname = "non-maskable interrupt"; - break; - case RX_EXCP_TRAP_BASE ... RX_EXCP_TRAP_BASE + RX_EXCP_TRAP_COUNT - 1: - expname = "unconditional trap"; - } qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", - (vec & 0xff), expname); + (vec & 0xff), rx_exception_name(vec)); } env->regs[0] = env->isp; } -- 2.55.0