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From: Shrikanth Hegde <sshegde@linux.ibm.com>
To: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org,
	peterz@infradead.org, tim.c.chen@linux.intel.com
Cc: sshegde@linux.ibm.com, christophe.leroy@csgroup.eu,
	linux-kernel@vger.kernel.org, ritesh.list@gmail.com,
	kprateek.nayak@amd.com, yu.c.chen@intel.com,
	vineethr@linux.ibm.com, vincent.guittot@linaro.org,
	srikar@linux.ibm.com, npiggin@gmail.com, mpe@ellerman.id.au
Subject: [PATCH 2/4] powerpc/topology: Add docs for llc_override
Date: Mon, 12 Oct 2026 15:50:35 +0530	[thread overview]
Message-ID: <20261012102037.2477378-3-sshegde@linux.ibm.com> (raw)
In-Reply-To: <20261012102037.2477378-1-sshegde@linux.ibm.com>

Provide documentation for the newly introduced debug knob
named as llc_override.

This may help one if they want to experiment with cache aware
scheduling.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 Documentation/arch/powerpc/index.rst    |  1 +
 Documentation/arch/powerpc/topology.rst | 27 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/arch/powerpc/topology.rst

diff --git a/Documentation/arch/powerpc/index.rst b/Documentation/arch/powerpc/index.rst
index 40419bea8e10..0f4caf50a9e7 100644
--- a/Documentation/arch/powerpc/index.rst
+++ b/Documentation/arch/powerpc/index.rst
@@ -33,6 +33,7 @@ powerpc
     qe_firmware
     syscall64-abi
     transactional_memory
+    topology
     ultravisor
     vas-api
     vcpudispatch_stats
diff --git a/Documentation/arch/powerpc/topology.rst b/Documentation/arch/powerpc/topology.rst
new file mode 100644
index 000000000000..9ed3cf7ade69
--- /dev/null
+++ b/Documentation/arch/powerpc/topology.rst
@@ -0,0 +1,27 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. _topology:
+
+
+llc_override
+==============
+
+Override the scheduler-visible LLC domain on PowerPC.
+
+Having LLC(last level cache) at MC/PKG helps to experiment with new
+scheduler feature called cache aware scheduling which expects LLC to have
+at least more than 1 core. Scheduler uses notion of LLC for wakeup and
+load balancing decisions.
+
+Accepted values are:
+
+  0    Disable the override and use the platform default.
+  smt  LLC will be at SMT domain.
+  mc   LLC will be at MC domain, including at SMT domains.
+  pkg  LLC will be at PKG domain, including at MC and SMT domains,
+
+Writing a new value rebuilds the scheduler domains. One can check the
+domain flags and look for SD_SHARE_LLC to confirm if it took effect.
+
+Note that this doesn't change HW cache topology. It is only a debug knob
+to experiment with scheduler related functionalities. So set it to sensible
+values. Also note that there is no performance guarantees across the values.
-- 
2.52.0



  parent reply	other threads:[~2026-10-12 10:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-12 10:20 [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs Shrikanth Hegde
2026-10-12 10:20 ` [PATCH 1/4] powerpc/topology: Introduce llc_override debug knob Shrikanth Hegde
2026-10-12 12:14   ` Srikar Dronamraju
2026-10-12 14:10     ` Shrikanth Hegde
2026-10-12 10:20 ` Shrikanth Hegde [this message]
2026-10-12 10:20 ` [PATCH 3/4] powerpc/topology: Update mc/pkg flags based on llc_override Shrikanth Hegde
2026-10-12 10:20 ` [PATCH 4/4] powerpc/topology: Rebuild sched domains on llc_override change Shrikanth Hegde
2026-10-12 12:19 ` [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs Srikar Dronamraju
2026-10-12 14:14   ` Shrikanth Hegde
2026-10-12 21:15 ` Tim Chen
2026-10-13  9:58   ` Shrikanth Hegde
2026-10-13 20:44     ` Tim Chen
2026-10-14  3:16       ` Shrikanth Hegde
2026-10-14  3:56         ` Srikar Dronamraju
2026-10-14  4:18           ` Shrikanth Hegde
2026-10-13 10:05   ` Chen, Yu C

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