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From: Tathagat Priyadarshi <tathagat.dpdk@gmail.com>
To: dev@dpdk.org
Cc: joshwash@google.com, stable@dpdk.org
Subject: [PATCH 3/4] net/gve: add cacheline overlap margin to DQO TX ring
Date: Mon, 12 Oct 2026 10:50:22 +0000	[thread overview]
Message-ID: <20261012105023.669486-4-tathagat.dpdk@gmail.com> (raw)
In-Reply-To: <20261012105023.669486-1-tathagat.dpdk@gmail.com>

The GVNIC DQO hardware DMA engine prefetches descriptors in cacheline
units (64 bytes = 4 descriptors of 16 bytes each). When producer tail
and consumer head indices share a cacheline, CPU and device DMA memory
collisions can occur.

Align with the Linux driver (gve_has_tx_slots_available()) by requiring
GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP (4 descriptors) headroom when
checking descriptor availability before enqueueing packets.

Fixes: 4022f9999f56 ("net/gve: support basic Tx data path for DQO")
Cc: stable@dpdk.org

Acked-by: Joshua Washington <joshwash@google.com>
Signed-off-by: Tathagat Priyadarshi <tathagat.dpdk@gmail.com>
---
 drivers/net/gve/gve_tx_dqo.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
index a8382ff3c4..9210b02eb1 100644
--- a/drivers/net/gve/gve_tx_dqo.c
+++ b/drivers/net/gve/gve_tx_dqo.c
@@ -261,6 +261,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 	uint16_t nb_tx = 0;
 	uint64_t bytes = 0;
 	uint64_t ol_flags;
+	uint16_t req_descs;
 	uint16_t nb_descs;
 	bool csum, tso;
 	uint16_t tx_id;
@@ -291,14 +292,17 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 
 		nb_descs = gve_tx_pkt_nb_data_descs(tx_pkt);
 		nb_descs += tso;
+		req_descs = nb_descs + GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP;
 
-		/* Clean if there aren't enough descriptors to send the packet. */
-		if (unlikely(!gve_can_tx(txq, nb_descs, 1))) {
+		/* Clean if there aren't enough descriptors to send the packet
+		 * while maintaining the cacheline overlap margin.
+		 */
+		if (unlikely(!gve_can_tx(txq, req_descs, 1))) {
 			int nb_to_clean = RTE_MAX(DQO_TX_MULTIPLIER * txq->rs_thresh,
-						  nb_descs);
+						  (int)req_descs);
 
 			gve_tx_clean_descs_dqo(txq, nb_to_clean);
-			if (!gve_can_tx(txq, nb_descs, 1))
+			if (!gve_can_tx(txq, req_descs, 1))
 				break;
 		}
 
-- 
2.43.0


  parent reply	other threads:[~2026-10-12 20:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-12 10:50 [PATCH 0/4] net/gve: fix TX queue stalls and sync DQO RDA with Linux driver Tathagat Priyadarshi
2026-10-12 10:50 ` [PATCH 1/4] net/gve: fix DQO descriptor cleaning loop bound Tathagat Priyadarshi
2026-10-12 10:50 ` [PATCH 2/4] net/gve: fix DQO TX queue stall on multi-seg and TSO Tathagat Priyadarshi
2026-10-12 18:13   ` Joshua Washington
2026-10-12 10:50 ` Tathagat Priyadarshi [this message]
2026-10-12 10:50 ` [PATCH 4/4] net/gve: add packet and TSO hardware constraints for DQO Tathagat Priyadarshi
2026-10-12 19:40   ` Joshua Washington
2026-10-12 21:28 ` [PATCH 0/4] net/gve: fix TX queue stalls and sync DQO RDA with Linux driver Stephen Hemminger
2026-10-13 10:43 ` [PATCH v2 0/4] net/gve: fix Tx " Tathagat Priyadarshi
2026-10-13 10:43   ` [PATCH v2 1/4] net/gve: fix DQO descriptor cleaning loop bound Tathagat Priyadarshi
2026-10-13 10:43   ` [PATCH v2 2/4] net/gve: fix DQO Tx queue stall on multi-seg and TSO Tathagat Priyadarshi
2026-10-14  0:30     ` Joshua Washington
2026-10-13 10:43   ` [PATCH v2 3/4] net/gve: add cacheline overlap margin to DQO Tx ring Tathagat Priyadarshi
2026-10-13 10:43   ` [PATCH v2 4/4] net/gve: add packet and TSO hardware constraints for DQO Tathagat Priyadarshi
2026-10-14  0:50     ` Joshua Washington
2026-10-13 15:22   ` [PATCH v2 0/4] net/gve: fix Tx queue stalls and sync DQO RDA with Linux driver Stephen Hemminger

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