From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE44B38B125; Tue, 13 Oct 2026 11:56:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791892580; cv=none; b=enlvP9EGAn4XbXV5b4l7n79nZtvVbE/qsIyDldRQxGiYP5a1/TTZ9DWU4M4lwlJZ/XWXcvxcydnXpKvr+TnJ1IKC8hJU0wDsEEANtD0PluxXdyJlr9Th92h/GmMTHqQNUBl+hJcvpjILNpmEUOwOidl9LjnmbqRYyr95Naayw5M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791892580; c=relaxed/simple; bh=g1kF5G1SQlCNJAklyhRLu4IhDFllQq/s5kjivKW7gcQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YF/JHm6b26j+Q5ieNbjBzzcf1CrJJkXLhRiY6G9EVbAmbNMwfX/stchbAptQ78ezTFsz0Tm+ili/+wYkzdh7TYG3JO7HmEHcBu46FzSJkejhij2weNrWzfcORrVtoa6fIocttwnwVjgcCb1Bkw+BiQWbHl7fsmiEpJNJ/VUZwPI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=YSTluWKP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="YSTluWKP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46AD41F000FF; Tue, 13 Oct 2026 11:56:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1791892578; bh=k9+xWW4RQxkOIVSAzPfPvSFq7JDi+agYsnYeOov2de8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=YSTluWKPiWHKZ9U2zXhscRN9Hwryvbs8jLNDKCTEnEZxqpKksoxf2dOVN786bM3KH pkbKojgf0QgXJA73mXAdwie7Ybnu2R7zp5gYLnYOdRfO99GzGQX/xAPvSOh2maCqca nogCWqyYOTiR2v/F7UBtNWQ+WWxVpKP2dak8jceE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Luca Weiss , Abel Vesa , Bjorn Andersson , Sasha Levin Subject: [PATCH 7.2 176/281] clk: qcom: gcc-eliza: Fix always-enabling PCIE_RSCC clocks Date: Tue, 13 Oct 2026 13:38:12 +0200 Message-ID: <20261013112859.437619817@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261013112855.045212108@linuxfoundation.org> References: <20261013112855.045212108@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.2-stable review patch. If anyone has any objections, please let me know. ------------------ From: Luca Weiss [ Upstream commit 5ffd02d16f4e2f0566b8f31d5610538987e1944c ] The critical_cbrcrs array will get qcom_branch_set_clk_en() called on each entry which will set BIT(0) to enable the clock. This is however wrong for these two PCIE_RSCC clocks which need BIT(20) and BIT(21) set respectively to enable them. Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza") Signed-off-by: Luca Weiss Tested-by: Abel Vesa Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260807-various-pcie-clk-fix-v1-1-5caf78a599d7@fairphone.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/gcc-eliza.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c index 3e26c7a1e5b54..fe18942a59ac4 100644 --- a/drivers/clk/qcom/gcc-eliza.c +++ b/drivers/clk/qcom/gcc-eliza.c @@ -3010,8 +3010,6 @@ static const u32 gcc_eliza_critical_cbcrs[] = { 0x26034, /* GCC_CAMERA_XO_CLK */ 0x27004, /* GCC_DISP_AHB_CLK */ 0x71004, /* GCC_GPU_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ - 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 0x32004, /* GCC_VIDEO_AHB_CLK */ 0x32038, /* GCC_VIDEO_XO_CLK */ }; @@ -3045,6 +3043,10 @@ static const struct regmap_config gcc_eliza_regmap_config = { static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap) { + /* Keep clocks always enabled */ + regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20)); /* GCC_PCIE_RSCC_CFG_AHB_CLK */ + regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21)); /* GCC_PCIE_RSCC_XO_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); -- 2.53.0