From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4240147CA69; Tue, 13 Oct 2026 11:55:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791892501; cv=none; b=CVrXmtTXdd1UBvgB4NbbDUqiIQP9rXOa7s23BT+nmAohrG5yqhfxR5OqjJ3mW7iGd3zLriFDUD9pcdoNcRBi7CEN7ncHnldWaHXTFybN773sX9Rn+6MBl3vo38f3rSbiqmA8YMhFhGdBmMUFyECA+aOF5Soev1YOlevCrBswDzE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791892501; c=relaxed/simple; bh=eJhJ1OWga/P3+ixVOsS2+webOqE/nNzMgksbg97HHto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kcn+gnQt2pq/H7CsTIKCJZq6CYsJVRQZ5mrsM6Km4BGCoHAD6LU0L6UfyTcfHjExpuSjwzXwk2zpHzFjxMCYZF4i3Jyr5GZn2p2Yg+LP1mWyks5a+ZEEFbICz5XqehfHheg31sJp51FS5wnM0r2lQPkZURKk7NGoYVf4M5F8D2E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=QFnsiF/T; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="QFnsiF/T" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99F8C1F000FF; Tue, 13 Oct 2026 11:54:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1791892500; bh=JW9PToY/8GxEltPIimbjy9jydEC9xs1dzAnhMXEGQaU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QFnsiF/TUf9t/CxjO6dilBo82SWu6AQv0ZoNsUH/nTG3DQ8dYbxDpNNyGIqc5K+Sf K6HhkntRYOjyNv0KsoGW5pnOInllWyI2vCc5OJ61JNniHCEKqCKSLrrJxEuKfOJS4G qeM5kHzQ47hjCSBxbjtAs9l2aIso8CeKxVRP9qhc= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ijae Kim , Myeonghun Pak , Thomas Zimmermann , Sasha Levin Subject: [PATCH 7.2 194/281] drm/aspeed: Balance the display clock enable on teardown Date: Tue, 13 Oct 2026 13:38:30 +0200 Message-ID: <20261013112859.872938779@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261013112855.045212108@linuxfoundation.org> References: <20261013112855.045212108@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.2-stable review patch. If anyone has any objections, please let me know. ------------------ From: Myeonghun Pak [ Upstream commit ecce445c6489895463b7ddec2af66338287fee4c ] aspeed_gfx_load() enables the display clock without checking the return value and never disables it on probe failure or removal. devm_clk_get() only releases the clock reference, leaving the enable unbalanced. Use devm_clk_get_enabled() to handle enable failures and automatically disable and unprepare the clock on probe failure or removal. This issue was identified during our ongoing static-analysis research while reviewing kernel code. Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver") Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak Assisted-by: OpenAI:GPT-5.6 Reviewed-by: Thomas Zimmermann Signed-off-by: Thomas Zimmermann Link: https://patch.msgid.link/20260913223019.89651-1-mhun512@gmail.com Link: https://patch.msgid.link/20260905080426.34224-1-kmehltretter@gmail.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index d4577663a1f0e..aa36b79d0f6c4 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -189,13 +189,12 @@ static int aspeed_gfx_load(struct drm_device *drm) } reset_control_deassert(priv->rst); - priv->clk = devm_clk_get(drm->dev, NULL); + priv->clk = devm_clk_get_enabled(drm->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, - "missing or invalid clk device tree entry"); + "failed to get and enable clock\n"); return PTR_ERR(priv->clk); } - clk_prepare_enable(priv->clk); /* Sanitize control registers */ writel(0, priv->base + CRT_CTRL1); -- 2.53.0