From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8482A360EC5; Tue, 13 Oct 2026 12:52:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791895974; cv=none; b=UB3Rz5+E1vsTQ7e69sz6QdqlPrE+8XN+NAuHfAxYoP2Ebk8I0XeA2O21HS0JmHI1QvtN1qsy5WYlebBEL7kbBDUDk1iDIRnNqwz390T3ZYZgdXp9dueiOvCyamddvy0qGHbC73U4u5SsTo2kHbJHFaWtqQjd+VCoAQJuyYSGSC4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791895974; c=relaxed/simple; bh=7p7gdQjp+JWfwAEsP1Vabq+8el7rmid2PXs9CrQX7m0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tin5kCZnCU96SECe43r5Id5THryQhoH9ftJirvfQ5x2n2sacayLot29ZFxeG+PCtYUNs6eMjJrUBxXLP/skkiq/c8Rgup+ri4mWarI8IpJ4/51myJY4+wstv3dejontlPWiviDqlin0AKMWQsJAlnH6y1ytYF43UQE+SnCTiN4c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=LbXAi2w1; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="LbXAi2w1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D95CB1F00893; Tue, 13 Oct 2026 12:52:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1791895973; bh=WE0u37hi1YEmgKNhoIBT63fa6AhjURU/UVWJ4TU9IQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LbXAi2w1TvteuL3lZsB0i7h0Nk/KSf/HalorTkg0oQLr2N5AykObPDRed2Re8NQdj hAPdqTT33ocNhP/mD68oju2e8H90BD/tLYvWemA3NCA344ol5JTzSm0/jUF/yvmR1j 5WNqKyNJXGsnBiUOdUTpa6n9ZBJ5wqQn7V3rrUZE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Ijae Kim , Myeonghun Pak , Thomas Zimmermann , Sasha Levin Subject: [PATCH 6.12 453/497] drm/aspeed: Balance the display clock enable on teardown Date: Tue, 13 Oct 2026 13:40:20 +0200 Message-ID: <20261013112918.633771584@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261013112907.864180619@linuxfoundation.org> References: <20261013112907.864180619@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Myeonghun Pak [ Upstream commit ecce445c6489895463b7ddec2af66338287fee4c ] aspeed_gfx_load() enables the display clock without checking the return value and never disables it on probe failure or removal. devm_clk_get() only releases the clock reference, leaving the enable unbalanced. Use devm_clk_get_enabled() to handle enable failures and automatically disable and unprepare the clock on probe failure or removal. This issue was identified during our ongoing static-analysis research while reviewing kernel code. Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver") Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak Assisted-by: OpenAI:GPT-5.6 Reviewed-by: Thomas Zimmermann Signed-off-by: Thomas Zimmermann Link: https://patch.msgid.link/20260913223019.89651-1-mhun512@gmail.com Link: https://patch.msgid.link/20260905080426.34224-1-kmehltretter@gmail.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c index a7a6b70220eb8..bf0a2268982e9 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -191,13 +191,12 @@ static int aspeed_gfx_load(struct drm_device *drm) } reset_control_deassert(priv->rst); - priv->clk = devm_clk_get(drm->dev, NULL); + priv->clk = devm_clk_get_enabled(drm->dev, NULL); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, - "missing or invalid clk device tree entry"); + "failed to get and enable clock\n"); return PTR_ERR(priv->clk); } - clk_prepare_enable(priv->clk); /* Sanitize control registers */ writel(0, priv->base + CRT_CTRL1); -- 2.53.0