From: "Michał Grzelak" <michal.grzelak@linux.intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: "Michał Grzelak" <michal.grzelak@linux.intel.com>,
"Jani Nikula" <jani.nikula@intel.com>
Subject: [PATCH v4 1/5] drm/i915/display: clean SKL_DSSM register macros
Date: Tue, 13 Oct 2026 22:47:00 +0200 [thread overview]
Message-ID: <20261013204705.1574475-2-michal.grzelak@linux.intel.com> (raw)
In-Reply-To: <20261013204705.1574475-1-michal.grzelak@linux.intel.com>
Indent SKL_DSSM register macros. Define mask and register values with
REG_GENMASK() and REG_FIELD_PREP() instead of bit shifts. No functional
change.
v2->v3
- s/fix/clean/ (Jani)
v1->v2
- s/REG_GENMASK/REG_FIELD_PREP/ (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Michał Grzelak <michal.grzelak@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 8251ec15190b..0b3991bc3aef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1779,10 +1779,10 @@
#define XE2LPD_DE_CAP_SCALER_SINGLE 1
#define SKL_DSSM _MMIO(0x51004)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
-#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 0)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 1)
+#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 2)
/*GEN11 chicken */
#define _PIPEA_CHICKEN 0x70038
--
2.45.2
next prev parent reply other threads:[~2026-10-13 20:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 20:46 [PATCH v4 0/5] SKL_DSSM / DE_CAP cleanup Michał Grzelak
2026-10-13 20:47 ` Michał Grzelak [this message]
2026-10-13 20:47 ` [PATCH v4 2/5] drm/i915/3dlut: disable 3D LUT for pre-GLK Michał Grzelak
2026-10-13 20:59 ` sashiko-bot
2026-10-13 20:47 ` [PATCH v4 3/5] drm/i915/3dlut: log 3D LUT's status Michał Grzelak
2026-10-13 20:47 ` [PATCH v4 4/5] drm/i915/3dlut: disable 3D LUT if unsupported Michał Grzelak
2026-10-13 20:47 ` [PATCH v4 5/5] drm/i915/display: log eDP TC support and DBuf overlap detection state Michał Grzelak
2026-10-13 20:53 ` sashiko-bot
2026-10-13 21:24 ` ✗ CI.checkpatch: warning for SKL_DSSM / DE_CAP cleanup Patchwork
2026-10-13 21:26 ` ✓ CI.KUnit: success " Patchwork
2026-10-13 22:29 ` ✓ i915.CI.BAT: " Patchwork
2026-10-14 2:57 ` ✓ Xe.CI.BAT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261013204705.1574475-2-michal.grzelak@linux.intel.com \
--to=michal.grzelak@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.