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envelope-from=bin.meng@processmission.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Cadence SDHCI integrations can differ in whether they provide a 64-bit system bus. Advertising the capability unconditionally could make a guest select unsupported ADMA descriptors. Add a bus64bit property to the Cadence model and keep it disabled by default. When enabled, expose the corresponding capability through the generic SDHCI child. Signed-off-by: Bin Meng Tested-by: Conor Dooley --- (no changes since v2) Changes in v2: - Make 64-bit system bus support a device property include/hw/sd/cadence_sdhci.h | 1 + hw/sd/cadence_sdhci.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h index cd8288b7d8..553fa73842 100644 --- a/include/hw/sd/cadence_sdhci.h +++ b/include/hw/sd/cadence_sdhci.h @@ -34,6 +34,7 @@ typedef struct CadenceSDHCIState { MemoryRegion container; MemoryRegion iomem; BusState *bus; + bool bus64bit; uint32_t regs[CADENCE_SDHCI_NUM_REGS]; diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index 8476baf67f..875823a50d 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -25,6 +25,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "migration/vmstate.h" +#include "hw/core/qdev-properties.h" #include "hw/sd/cadence_sdhci.h" #include "sdhci-internal.h" @@ -147,6 +148,11 @@ static void cadence_sdhci_realize(DeviceState *dev, Error **errp) s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE); memory_region_add_subregion(&s->container, 0, &s->iomem); + if (s->bus64bit) { + object_property_set_uint(OBJECT(&s->sdhci), "capareg", + SDHC_CAPAB_REG_DEFAULT | + R_SDHC_CAPAB_BUS64BIT_MASK, &error_abort); + } sysbus_realize(sbd_sdhci, errp); memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE, sysbus_mmio_get_region(sbd_sdhci, 0)); @@ -165,6 +171,10 @@ static const VMStateDescription vmstate_cadence_sdhci = { }, }; +static const Property cadence_sdhci_properties[] = { + DEFINE_PROP_BOOL("bus64bit", CadenceSDHCIState, bus64bit, false), +}; + static void cadence_sdhci_class_init(ObjectClass *classp, const void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -172,6 +182,7 @@ static void cadence_sdhci_class_init(ObjectClass *classp, const void *data) dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; dc->realize = cadence_sdhci_realize; device_class_set_legacy_reset(dc, cadence_sdhci_reset); + device_class_set_props(dc, cadence_sdhci_properties); dc->vmsd = &vmstate_cadence_sdhci; } -- 2.53.0